xtensa: mmu: always map data TLB for VECBASE

This adds code to always map data TLB for VECBASE so that
we would be dealing with fewer data TLB misses during
exception handling. With VECBASE always mapped, there is
no need to pre-load anymore.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>

arch/xtensa/core/xtensa_mmu.c

@@ -19,6 +19,9 @@
 /* Fixed data TLB way to map the page table */
 #define MMU_PTE_WAY 7
 
+/* Fixed data TLB way to map VECBASE */
+#define MMU_VECBASE_WAY 8
+
 /* Level 1 contains page table entries
  * necessary to map the page table itself.
  */
@@ -283,6 +286,12 @@ static void xtensa_mmu_init(bool is_core0)
 				:: [idx] "a"((entry << 29) | 6));
 	}
 
+	/* Map VECBASE to a fixed data TLB */
+	xtensa_dtlb_entry_write(
+			Z_XTENSA_PTE((uint32_t)vecbase,
+				     MMU_KERNEL_RING, Z_XTENSA_MMU_CACHED_WB),
+			Z_XTENSA_TLB_ENTRY((uint32_t)vecbase, MMU_VECBASE_WAY));
+
 	/* To finish, just restore vecbase and invalidate TLB entries
 	 * used to map the relocated vecbase.
 	 */
@@ -308,10 +317,6 @@ static void xtensa_mmu_init(bool is_core0)
 		Z_XTENSA_PTE(vecbase, MMU_KERNEL_RING,
 			Z_XTENSA_MMU_X | Z_XTENSA_MMU_CACHED_WT),
 		Z_XTENSA_AUTOFILL_TLB_ENTRY(vecbase));
-	xtensa_dtlb_entry_write_sync(
-		Z_XTENSA_PTE(vecbase, MMU_KERNEL_RING,
-			Z_XTENSA_MMU_X | Z_XTENSA_MMU_CACHED_WT),
-		Z_XTENSA_AUTOFILL_TLB_ENTRY(vecbase));
 }
 
 void z_xtensa_mmu_init(void)

arch/xtensa/include/xtensa-asm2-s.h

@@ -562,15 +562,6 @@ _Level\LVL\()Vector:
 	/* Preload PTE entry page of current stack. */
 	PRELOAD_PTEVADDR a3, a2
 
-	/* Preload PTE entry page of VECBASE. This is due to
-	 * _handle_excint_imm* and _c_handler_imm* (below).
-	 * We cannot afford a TLB miss while already handling
-	 * an exception. So make sure the VECBASE page is
-	 * mapped in TLB.
-	 */
-	rsr.vecbase a2
-	PRELOAD_PTEVADDR a3, a2
-
 	/* Preload PTE entry page of new stack, where
 	 * it will be used later (in EXCINT_HANDLER above).
 	 */