soc: riscv: esp32c3: use the new esp_rom prefix

For esp32c3 related ROM located functions instead of esp32c3_rom. Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com> Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
tobias-roehmel · Jul 8, 2021 · 600f8c6 · 600f8c6
1 parent 2d1bdd8
commit 600f8c6
Show file tree

Hide file tree

Showing 3 changed files with 14 additions and 14 deletions.
diff --git a/drivers/timer/esp32c3_sys_timer.c b/drivers/timer/esp32c3_sys_timer.c
@@ -30,7 +30,7 @@ int sys_clock_driver_init(const struct device *dev)
 {
 	ARG_UNUSED(dev);
 
-	esp32c3_rom_intr_matrix_set(0,
+	esp_rom_intr_matrix_set(0,
 		ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,
 		SYS_TIMER_CPU_IRQ);
 	IRQ_CONNECT(SYS_TIMER_CPU_IRQ, 0, sys_timer_isr, NULL, 0);

diff --git a/soc/riscv/esp32c3/soc.c b/soc/riscv/esp32c3/soc.c
@@ -78,7 +78,7 @@ void __attribute__((section(".iram1"))) __start(void)
 #endif
 
 	/* Configure the Cache MMU size for instruction and rodata in flash. */
-	extern uint32_t esp32c3_rom_cache_set_idrom_mmu_size(uint32_t irom_size,
+	extern uint32_t esp_rom_cache_set_idrom_mmu_size(uint32_t irom_size,
 			uint32_t drom_size);
 
 	extern int _rodata_reserved_start;
@@ -88,7 +88,7 @@ void __attribute__((section(".iram1"))) __start(void)
 		((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) *
 			sizeof(uint32_t);
 
-	esp32c3_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size,
+	esp_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size,
 		CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
 
 	/* set global esp32c3's INTC masking level */
@@ -104,9 +104,9 @@ void __attribute__((section(".iram1"))) __start(void)
 int IRAM_ATTR arch_printk_char_out(int c)
 {
 	if (c == '\n') {
-		esp32c3_rom_uart_tx_one_char('\r');
+		esp_rom_uart_tx_one_char('\r');
 	}
-	esp32c3_rom_uart_tx_one_char(c);
+	esp_rom_uart_tx_one_char(c);
 	return 0;
 }
 
@@ -116,9 +116,9 @@ void IRAM_ATTR esp_restart_noos(void)
 	csr_read_clear(mstatus, MSTATUS_MIE);
 
 	/* Flush any data left in UART FIFOs */
-	esp32c3_rom_uart_tx_wait_idle(0);
-	esp32c3_rom_uart_tx_wait_idle(1);
-	esp32c3_rom_uart_tx_wait_idle(2);
+	esp_rom_uart_tx_wait_idle(0);
+	esp_rom_uart_tx_wait_idle(1);
+	esp_rom_uart_tx_wait_idle(2);
 
 	/* 2nd stage bootloader reconfigures SPI flash signals. */
 	/* Reset them to the defaults expected by ROM */

diff --git a/soc/riscv/esp32c3/soc.h b/soc/riscv/esp32c3/soc.h
@@ -34,12 +34,12 @@
 
 #ifndef _ASMLANGUAGE
 
-extern void esp32c3_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
-extern void esp32c3_rom_uart_attach(void);
-extern void esp32c3_rom_uart_tx_wait_idle(uint8_t uart_no);
-extern STATUS esp32c3_rom_uart_tx_one_char(uint8_t chr);
-extern STATUS esp32c3_rom_uart_rx_one_char(uint8_t *chr);
-extern void esp32c3_rom_ets_set_user_start(uint32_t start);
+extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
+extern void esp_rom_uart_attach(void);
+extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
+extern STATUS esp_rom_uart_tx_one_char(uint8_t chr);
+extern STATUS esp_rom_uart_rx_one_char(uint8_t *chr);
+extern void esp_rom_ets_set_user_start(uint32_t start);
 
 ulong_t __soc_get_gp_initial_value(void);