soc: xtensa: esp32_net:

Fixes boot sequence for esp32_net, also reflect the changes in the esp32 ipm driver. Signed-off-by: Felipe Neves <felipe.neves@linaro.org>
tobias-roehmel · Oct 19, 2022 · 5760fcc · 5760fcc
1 parent 6fae7a1
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Showing 7 changed files with 1,838 additions and 1,852 deletions.
diff --git a/drivers/ipm/ipm_esp32.c b/drivers/ipm/ipm_esp32.c
@@ -234,7 +234,7 @@ static const struct ipm_driver_api esp32_ipm_driver_api = {
 										\
 static struct esp32_ipm_config esp32_ipm_device_cfg_##idx = {	\
 	.irq_source_pro_cpu = DT_INST_IRQN(idx),		\
-	.irq_source_pro_cpu = DT_INST_IRQN(idx) + 1,	\
+	.irq_source_app_cpu = DT_INST_IRQN(idx) + 1,	\
 };	\
 	\
 static struct esp32_ipm_data esp32_ipm_device_data_##idx = {	\

diff --git a/samples/drivers/ipm/ipm_esp32/README.rst b/samples/drivers/ipm/ipm_esp32/README.rst
@@ -21,18 +21,8 @@ messages in chunks of 64bytes.
 Building and Running the Zephyr Code
 ************************************
 
-The sample requires two build commands to run, for that reason a pre built
-version of esp32_net, the APP cpu side firmware is already provided for quick
-tests just type on the console:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/drivers/ipm/ipm_esp32
-   :board: esp32
-   :goals: build flash
-   :compact:
-
-The other option is building from scratch just involve a single extra build command
-and file moving, first of all you need to build the esp32_net firmware as follows:
+The sample requires two build commands to run, first of all
+you need to build the esp32_net firmware as follows:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/drivers/ipm/ipm_esp32/ipm_esp32_net

diff --git a/samples/drivers/ipm/ipm_esp32/src/esp32_net_firmware.c b/samples/drivers/ipm/ipm_esp32/src/esp32_net_firmware.c
diff --git a/soc/xtensa/esp32/esp32-mp.c b/soc/xtensa/esp32/esp32-mp.c
@@ -194,6 +194,26 @@ void esp_appcpu_start(void *entry_point)
 	DPORT_APPCPU_CTRL_A |= DPORT_APPCPU_RESETTING;
 	DPORT_APPCPU_CTRL_A &= ~DPORT_APPCPU_RESETTING;
 
+
+	/* extracted from SMP LOG above, THIS IS REQUIRED FOR AMP RELIABLE
+	 * OPERATION AS WELL, PLEASE DON'T touch on the dummy write below!
+	 *
+	 * Note that the logging done here is ACTUALLY REQUIRED FOR RELIABLE
+	 * OPERATION!  At least one particular board will experience spurious
+	 * hangs during initialization (usually the APPCPU fails to start at
+	 * all) without these calls present.  It's not just time -- careful
+	 * use of k_busy_wait() (and even hand-crafted timer loops using the
+	 * Xtensa timer SRs directly) that duplicates the timing exactly still
+	 * sees hangs.  Something is happening inside the ROM UART code that
+	 * magically makes the startup sequence reliable.
+	 *
+	 * Leave this in place until the sequence is understood better.
+	 *
+	 */
+	esp_rom_uart_tx_one_char('\r');
+	esp_rom_uart_tx_one_char('\r');
+	esp_rom_uart_tx_one_char('\n');
+
 	/* Seems weird that you set the boot address AFTER starting
 	 * the CPU, but this is how they do it...
 	 */

diff --git a/soc/xtensa/esp32/soc.c b/soc/xtensa/esp32/soc.c
@@ -125,9 +125,6 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
 	/* start the esp32 network core before
 	 * start zephyr
 	 */
-	soc_ll_stall_core(1);
-	soc_ll_reset_core(1);
-	DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
 	start_esp32_net_cpu();
 #endif