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[WebAssembly] Select BUILD_VECTOR with large unsigned lane values
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Previously we expected lane constants to be in the range of signed values for
each lane size, but the included test case produced large unsigned values that
fall outside that range. Allow instruction selection to proceed in this case
rather than failing.

Fixes llvm#63817.
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tlively committed Mar 20, 2024
1 parent 12a2bc3 commit ef9339e
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Showing 2 changed files with 19 additions and 2 deletions.
6 changes: 4 additions & 2 deletions llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
Original file line number Diff line number Diff line change
Expand Up @@ -46,10 +46,12 @@ defm "" : ARGUMENT<V128, v2i64>;
defm "" : ARGUMENT<V128, v4f32>;
defm "" : ARGUMENT<V128, v2f64>;

// Constrained immediate argument types
// Constrained immediate argument types. Allow any value from the minimum signed
// value to the maximum unsigned value for the lane size.
foreach SIZE = [8, 16] in
def ImmI#SIZE : ImmLeaf<i32,
"return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));"
// -2^(n-1) <= Imm <= 2^n-1, avoiding UB when n == 64.
"return -(1 << ("#SIZE#" - 1)) <= Imm && Imm <= int64_t(uint64_t(1 << ("#SIZE#" - 1) << 1) - 1);"
>;
foreach SIZE = [2, 4, 8, 16, 32] in
def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
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15 changes: 15 additions & 0 deletions llvm/test/CodeGen/WebAssembly/pr63817.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=wasm32 -mattr=+simd128 | FileCheck %s

;; Regression test for a bug in which BUILD_VECTOR nodes with large unsigned
;; lane constants were not properly selected.
define <4 x i8> @test(<4 x i8> %0) {
; CHECK-LABEL: test:
; CHECK: .functype test (v128) -> (v128)
; CHECK-NEXT: # %bb.0:
; CHECK-NEXT: v128.const 255, 17, 255, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK-NEXT: # fallthrough-return
%V1 = or <4 x i8> <i8 255, i8 255, i8 255, i8 255>, %0
%V2 = insertelement <4 x i8> %V1, i8 17, i32 1
ret <4 x i8> %V2
}

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