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[skip ci] Fix bug in uintr: save uepc
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田凯夫 committed Mar 24, 2023
1 parent 0cd32e4 commit 4486190
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Showing 6 changed files with 31 additions and 8 deletions.
3 changes: 2 additions & 1 deletion kernel/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -42,4 +42,5 @@ uintr = { path = "../crates/uintr" }
default = ["oscomp", "test"]
test = []
oscomp = []
uintr = []
uintr = []
sleeplock = []
6 changes: 5 additions & 1 deletion kernel/src/arch/riscv64/trap/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,9 @@ pub fn enable_timer_intr() {
/// 2. Handles page fault caused by Instruction Fetch, Load or Store.
#[no_mangle]
pub fn user_trap_handler() -> ! {
#[cfg(feature = "uintr")]
uintr_save();

set_kernel_trap();

let scause = scause::read();
Expand Down Expand Up @@ -136,7 +139,8 @@ pub fn user_trap_handler() -> ! {
/// current task. We must drop them before changing the control flow without unwinding.
#[no_mangle]
pub fn user_trap_return() -> ! {
// crate::tests::sleeplock::test();
#[cfg(feature = "sleeplock")]
crate::tests::sleeplock::test();

#[cfg(feature = "uintr")]
uintr_return();
Expand Down
22 changes: 19 additions & 3 deletions kernel/src/arch/riscv64/uintr.rs
Original file line number Diff line number Diff line change
Expand Up @@ -182,6 +182,9 @@ pub struct TaskUIntrInner {

/// User interrupt handler
pub uscratch: usize,

/// User error pc
pub uepc: usize,
}

impl TaskUIntrInner {
Expand All @@ -192,6 +195,7 @@ impl TaskUIntrInner {
mask: 0,
utvec: 0,
uscratch: 0,
uepc: 0,
}
}

Expand Down Expand Up @@ -355,7 +359,11 @@ mod syscall {

/// Synchronize receiver status to UINTC and raise user interrupt if kernel returns to
/// a receiver with pending interrupt requests.
pub unsafe fn uirs_sync() {
///
/// Each time a receiver traps into a U-mode trap handler, it can be migrated to another hart
/// caused by U-ecall or other exceptions thus we must save and restore CPU-local registers such
/// as `upec`, `utvec` and `uscratch`.
pub unsafe fn uirs_restore() {
let uintr_inner = cpu().curr.as_ref().unwrap().uintr_inner();
if let Some(uirs) = &uintr_inner.uirs {
let index = uirs.0;
Expand All @@ -364,9 +372,10 @@ mod syscall {
uirs.mode |= 0x2; // 64 bits
uirs.sync(index);

log::trace!("uirs_sync {:x} {:x?}", index, uirs);
log::trace!("uirs_restore {:x} {:x?}", index, uirs);

// user configurations
uepc::write(uintr_inner.uepc);
utvec::write(uintr_inner.utvec, utvec::TrapMode::Direct);
uscratch::write(uintr_inner.uscratch);
uie::set_usoft();
Expand Down Expand Up @@ -400,12 +409,19 @@ mod syscall {
/// Called during trap return.
pub fn uintr_return() {
// receiver
unsafe { uirs_sync() };
unsafe { uirs_restore() };

// sender
uist_init();
}

/// Called when task traps into kernel.
pub fn uintr_save() {
let curr = cpu().curr.as_ref().unwrap();

curr.uintr_inner().uepc = uepc::read();
}

pub struct UIntrFile {
pub uirs_index: usize,
pub vector: usize,
Expand Down
2 changes: 1 addition & 1 deletion kernel/src/cons/logger.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ impl Log for Logger {
Level::Warn => 93, // BrightYellow
Level::Info => 34, // Blue
Level::Debug => 32, // Green
Level::Trace => 90, // BrightBlack
Level::Trace => 33, // BrightBlack
};
let cpu_id = get_cpu_id();
println!(
Expand Down
4 changes: 3 additions & 1 deletion kernel/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -76,9 +76,11 @@ pub extern "C" fn rust_main(hartid: usize) -> ! {
#[no_mangle]
pub extern "C" fn rust_main_others(hartid: usize) -> ! {
// Other initializations.

arch::init(hartid, false);
info!("(Secondary) Start executing tasks.");
// Enable timer interrupt
arch::trap::enable_timer_intr();
timer::set_next_trigger();
// IDLE loop
unsafe { task::idle() };
}
2 changes: 1 addition & 1 deletion test

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