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Factor out i64x2_mul
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haoyu-zc committed Jul 22, 2023
1 parent ca4a8b8 commit 35b631f
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Showing 2 changed files with 2 additions and 16 deletions.
9 changes: 1 addition & 8 deletions src/engine/x86-64/X86_64Interpreter.v3
Original file line number Diff line number Diff line change
Expand Up @@ -2423,6 +2423,7 @@ class X86_64InterpreterGen(ic: X86_64InterpreterCode, w: DataWriter) {
genSimdBinop(Opcode.I16X8_MUL, asm.pmullw_s_s);
genSimdBinop(Opcode.I32X4_MUL, asm.pmulld_s_s);
genSimdBinop(Opcode.I32X4_DOT_I16X8_S, asm.pmaddwd_s_s);
genSimdBinop(Opcode.I64X2_MUL, masm.emit_i64x2_mul(_, _, r_xmm2, r_xmm3));
genSimdBinop(Opcode.F32X4_ADD, asm.addps_s_s);
genSimdBinop(Opcode.F64X2_ADD, asm.addpd_s_s);
genSimdBinop(Opcode.F32X4_SUB, asm.subps_s_s);
Expand Down Expand Up @@ -2491,14 +2492,6 @@ class X86_64InterpreterGen(ic: X86_64InterpreterCode, w: DataWriter) {
genSimdBinop(Opcode.F32X4_MAX, masm.emit_f32x4_max(_, _, r_xmm2));
genSimdBinop(Opcode.F64X2_MAX, masm.emit_f64x2_max(_, _, r_xmm2));

bindHandler(Opcode.I64X2_MUL); {
asm.movdqu_s_m(r_xmm0, vsph[-2].value); // lhs, dst
asm.movdqu_s_m(r_xmm1, vsph[-1].value); // rhs
masm.emit_i64x2_mul(r_xmm0, r_xmm1, r_xmm2, r_xmm3);
asm.movdqu_m_s(vsph[-2].value, r_xmm0);
decrementVsp();
endHandler();
}

genSimdBinop(Opcode.I8X16_GT_S, asm.pcmpgtb_s_s);
genSimdBinop(Opcode.I16X8_GT_S, asm.pcmpgtw_s_s);
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9 changes: 1 addition & 8 deletions src/engine/x86-64/X86_64SinglePassCompiler.v3
Original file line number Diff line number Diff line change
Expand Up @@ -507,14 +507,7 @@ class X86_64SinglePassCompiler extends SinglePassCompiler {

def visit_I64X2_ADD() { do_op2_x_x(ValueKind.V128, asm.paddq_s_s); }
def visit_I64X2_SUB() { do_op2_x_x(ValueKind.V128, asm.psubq_s_s); }
def visit_I64X2_MUL() {
var b = popReg();
var a = popRegToOverwrite();
var t1 = allocTmp(ValueKind.V128);
var t2 = allocTmp(ValueKind.V128);
mmasm.emit_i64x2_mul(X(a.reg), X(b.reg), X(t1), X(t2));
state.push(a.kindFlagsMatching(ValueKind.V128, IN_REG), a.reg, 0);
}
def visit_I64X2_MUL() { do_op2_x_x(ValueKind.V128, mmasm.emit_i64x2_mul(_, _, X(allocTmp(ValueKind.V128)), X(allocTmp(ValueKind.V128)))); }
def visit_I64X2_NEG() { visit_V128_I_NEG(mmasm.emit_i64x2_neg); }
def visit_I64X2_EQ() { do_op2_x_x(ValueKind.V128, asm.pcmpeqq_s_s); }
def visit_I64X2_NE() { do_op2_x_x(ValueKind.V128, mmasm.emit_i64x2_ne); }
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