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@LJC00118 LJC00118 commented Oct 10, 2025

Summary by CodeRabbit

  • New Features
    • Added helper utilities to assemble packed FP8 vectors in E4 and E5 formats for sizes 2, 4, 8, 16, and 32. These constructors simplify creating and passing larger FP8 vector values from individual elements, improving FP8 data handling, readability, and consistency in GPU-related code paths.

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coderabbitai bot commented Oct 10, 2025

Walkthrough

Adds TL_DEVICE helper functions in src/tl_templates/cuda/cuda_fp8.h to construct packed FP8 vector types for both e4 and e5 formats at sizes 2, 4, 8, 16, and 32 elements, using recursive composition. No existing types modified; only new free functions returning constructed packed values.

Changes

Cohort / File(s) Summary
FP8 packer helpers
src/tl_templates/cuda/cuda_fp8.h
Introduces make_fp8_e4_{2,4,8,16,32}_t and make_fp8_e5_{2,4,8,16,32}_t functions that assemble packed vector structs from individual fp8 elements, composed hierarchically (e.g., 32 from two 16s).

Sequence Diagram(s)

sequenceDiagram
  autonumber
  participant U as Caller
  participant H as cuda_fp8.h
  rect rgba(230,240,255,0.5)
    note over U,H: Build fp8_e4_32_t via hierarchical packers
    U->>H: make_fp8_e4_32_t(x0..x15, y0..y15)
    activate H
    H->>H: make_fp8_e4_16_t(x0..x7, x8..x15)
    H->>H: make_fp8_e4_16_t(y0..y7, y8..y15)
    H-->>U: fp8_e4_32_t packed
    deactivate H
  end
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Estimated code review effort

🎯 2 (Simple) | ⏱️ ~10 minutes

Poem

A nibble, a byte, FP8 in a row,
I stack little pebbles where bitstreams flow.
Two into four, then eight into more—
Sixteen, thirty-two, neat bundles I store.
Thump goes my paw: pack, pack, hooray! 🥕🐇

Pre-merge checks and finishing touches

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✅ Passed checks (2 passed)
Check name Status Explanation
Description Check ✅ Passed Check skipped - CodeRabbit’s high-level summary is enabled.
Title Check ✅ Passed The title clearly and concisely summarizes the main change of adding pack functions for FP8 types in the CUDA context, which directly matches the new helper functions introduced in the pull request.
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Actionable comments posted: 2

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📒 Files selected for processing (1)
  • src/tl_templates/cuda/common.h (1 hunks)
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src/tl_templates/cuda/common.h (1)
src/tl_templates/cuda/cuda_fp8.h (9)
  • fp8_e4_2_t (9-12)
  • fp8_e4_4_t (14-19)
  • fp8_e4_8_t (21-24)
  • fp8_e5_16_t (61-64)
  • fp8_e4_32_t (31-42)
  • fp8_e5_2_t (44-47)
  • fp8_e5_4_t (49-54)
  • fp8_e5_8_t (56-59)
  • fp8_e5_32_t (66-77)
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src/tl_templates/cuda/common.h

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🔇 Additional comments (9)
src/tl_templates/cuda/common.h (9)

117-123: LGTM!

The function correctly packs two fp8_e4_t values into fp8_e4_2_t by direct field assignment.


125-132: LGTM!

The function correctly packs four fp8_e4_t values into fp8_e4_4_t by direct field assignment.


134-141: LGTM!

The function correctly packs eight fp8_e4_t values into fp8_e4_8_t by hierarchically composing two fp8_e4_4_t structures.


154-169: LGTM after the previous fix!

The function correctly packs thirty-two fp8_e4_t values into fp8_e4_32_t by hierarchically composing two fp8_e4_16_t structures. This will compile successfully once the make_fp8_e4_16_t function name is corrected.


171-177: LGTM!

The function correctly packs two fp8_e5_t values into fp8_e5_2_t by direct field assignment.


179-186: LGTM!

The function correctly packs four fp8_e5_t values into fp8_e5_4_t by direct field assignment.


188-195: LGTM!

The function correctly packs eight fp8_e5_t values into fp8_e5_8_t by hierarchically composing two fp8_e5_4_t structures.


197-206: LGTM!

The function correctly packs sixteen fp8_e5_t values into fp8_e5_16_t by hierarchically composing two fp8_e5_8_t structures.


208-223: LGTM!

The function correctly packs thirty-two fp8_e5_t values into fp8_e5_32_t by hierarchically composing two fp8_e5_16_t structures.

LeiWang1999
LeiWang1999 previously approved these changes Oct 10, 2025
@LeiWang1999 LeiWang1999 changed the title Add pack functions for FP8 types [CUDA] Add pack functions for FP8 types Oct 10, 2025
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Actionable comments posted: 1

♻️ Duplicate comments (1)
src/tl_templates/cuda/common.h (1)

148-159: Critical: Fix return type, parameter types, and function name (duplicate issue).

This function has multiple type consistency issues that were previously flagged but remain unfixed:

  1. Return type is fp8_e5_16_t but should be fp8_e4_16_t
  2. Parameters y6 and y7 at Lines 153-154 are declared as fp8_e5_t but should be fp8_e4_t
  3. Function name is make_fp8_e5_16_t but should be make_fp8_e4_16_t

The function body correctly uses fp8_e4_16_t and calls make_fp8_e4_8_t, indicating this is meant to pack e4 values, not e5. Additionally, make_fp8_e4_32_t at lines 171-174 calls make_fp8_e4_16_t, which does not exist due to the incorrect naming.

Apply this diff to fix the type mismatches and function name:

-// Pack sixteen fp8_e4_t values.
-TL_DEVICE fp8_e5_16_t make_fp8_e5_16_t(fp8_e4_t x0, fp8_e4_t x1, fp8_e4_t x2,
+// Pack sixteen fp8_e4_t values.
+TL_DEVICE fp8_e4_16_t make_fp8_e4_16_t(fp8_e4_t x0, fp8_e4_t x1, fp8_e4_t x2,
                                        fp8_e4_t x3, fp8_e4_t x4, fp8_e4_t x5,
                                        fp8_e4_t x6, fp8_e4_t x7, fp8_e4_t y0,
                                        fp8_e4_t y1, fp8_e4_t y2, fp8_e4_t y3,
-                                       fp8_e4_t y4, fp8_e4_t y5, fp8_e5_t y6,
-                                       fp8_e5_t y7) {
+                                       fp8_e4_t y4, fp8_e4_t y5, fp8_e4_t y6,
+                                       fp8_e4_t y7) {
   fp8_e4_16_t result;
   result.x = make_fp8_e4_8_t(x0, x1, x2, x3, x4, x5, x6, x7);
   result.y = make_fp8_e4_8_t(y0, y1, y2, y3, y4, y5, y6, y7);
   return result;
 }
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src/tl_templates/cuda/common.h (1)
src/tl_templates/cuda/cuda_fp8.h (9)
  • fp8_e4_2_t (9-12)
  • fp8_e4_4_t (14-19)
  • fp8_e4_8_t (21-24)
  • fp8_e5_16_t (61-64)
  • fp8_e4_32_t (31-42)
  • fp8_e5_2_t (44-47)
  • fp8_e5_4_t (49-54)
  • fp8_e5_8_t (56-59)
  • fp8_e5_32_t (66-77)
🔇 Additional comments (3)
src/tl_templates/cuda/common.h (3)

20-21: LGTM! Clear type aliases for FP8 types.

The type aliases provide convenient shorthand for the FP8 types and follow clear naming conventions.


119-146: LGTM! Pack functions follow consistent patterns.

The pack functions for 2, 4, and 8 element vectors are correctly implemented and follow a clear hierarchical pattern.


178-235: LGTM! All e5 pack functions are correctly implemented.

The e5 pack functions (2, 4, 8, 16, and 32 element variants) follow consistent patterns and have correct type signatures. They properly mirror the structure of the e4 pack functions.

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Actionable comments posted: 0

🧹 Nitpick comments (2)
src/tl_templates/cuda/cuda_fp8.h (2)

79-195: Consider adding __forceinline__ for consistency.

The existing assignment operators (lines 35-41, 70-76) use __device__ __forceinline__. For consistency and potential performance benefits, consider adding __forceinline__ to these packing functions, especially for the base cases (2 and 4 element packs) that are likely to be called frequently.

Example for make_fp8_e4_2_t:

-TL_DEVICE fp8_e4_2_t make_fp8_e4_2_t(fp8_e4_t x, fp8_e4_t y) {
+TL_DEVICE __forceinline__ fp8_e4_2_t make_fp8_e4_2_t(fp8_e4_t x, fp8_e4_t y) {

Apply similar changes to other packing functions if desired.


79-195: Consider adding tests for the new packing functions.

These new packing functions would benefit from unit tests to ensure correctness, especially for the larger packed types where the recursive composition could be prone to ordering errors.

Would you like me to help generate unit tests for these packing functions, or open a new issue to track this task?

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🔇 Additional comments (5)
src/tl_templates/cuda/cuda_fp8.h (5)

79-96: LGTM! Base packing functions are correctly implemented.

The make_fp8_e4_2_t and make_fp8_e4_4_t functions correctly pack individual FP8 values into their respective struct types, with field assignments matching the struct definitions.


98-136: LGTM! Recursive packing strategy is well-designed.

The functions make_fp8_e4_8_t, make_fp8_e4_16_t, and make_fp8_e4_32_t correctly use recursive composition to build larger packed types from smaller ones, matching the hierarchical structure of the underlying structs. The parameter distribution is correct.


138-155: LGTM! Base packing functions for e5 format are correctly implemented.

The make_fp8_e5_2_t and make_fp8_e5_4_t functions correctly pack individual FP8 e5m2 values, mirroring the structure of the e4m3 counterparts.


157-195: LGTM! Recursive packing for e5 format is correctly implemented.

The functions make_fp8_e5_8_t, make_fp8_e5_16_t, and make_fp8_e5_32_t correctly implement the same recursive composition strategy as their e4 counterparts, maintaining consistency across both FP8 formats.


79-195: No changes needed for TL_DEVICE macro
TL_DEVICE already expands to __forceinline__ __device__, satisfying both device and inlining requirements.

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Actionable comments posted: 0

🧹 Nitpick comments (2)
src/tl_templates/cuda/cuda_fp8.h (2)

79-138: LGTM! FP8 E4 pack functions are correctly implemented.

The recursive composition pattern is clean and the logic correctly maps input parameters to struct fields. However, note a minor style inconsistency and an AI summary discrepancy:

  1. The attribute ordering __forceinline__ __device__ differs from the existing code style __device__ __forceinline__ (see lines 35, 70). Consider maintaining consistency.
  2. The AI summary mentions __DEVICE__ decorator, but the actual code uses lowercase __device__.

Apply this diff to align with the existing code style:

-__forceinline__ __device__ fp8_e4_2_t make_fp8_e4_2_t(fp8_e4_t x, fp8_e4_t y) {
+__device__ __forceinline__ fp8_e4_2_t make_fp8_e4_2_t(fp8_e4_t x, fp8_e4_t y) {

-__forceinline__ __device__ fp8_e4_4_t make_fp8_e4_4_t(fp8_e4_t x0, fp8_e4_t x1,
+__device__ __forceinline__ fp8_e4_4_t make_fp8_e4_4_t(fp8_e4_t x0, fp8_e4_t x1,

-__forceinline__ __device__ fp8_e4_8_t make_fp8_e4_8_t(fp8_e4_t x0, fp8_e4_t x1,
+__device__ __forceinline__ fp8_e4_8_t make_fp8_e4_8_t(fp8_e4_t x0, fp8_e4_t x1,

-__forceinline__ __device__ fp8_e4_16_t
+__device__ __forceinline__ fp8_e4_16_t

-__forceinline__ __device__ fp8_e4_32_t make_fp8_e4_32_t(
+__device__ __forceinline__ fp8_e4_32_t make_fp8_e4_32_t(

140-199: LGTM! FP8 E5 pack functions correctly mirror the E4 implementation.

The e5 variant functions follow the same correct recursive composition pattern. The same style note applies regarding __forceinline__ __device__ vs __device__ __forceinline__ ordering for consistency with existing code.

Apply this diff to align with the existing code style:

-__forceinline__ __device__ fp8_e5_2_t make_fp8_e5_2_t(fp8_e5_t x, fp8_e5_t y) {
+__device__ __forceinline__ fp8_e5_2_t make_fp8_e5_2_t(fp8_e5_t x, fp8_e5_t y) {

-__forceinline__ __device__ fp8_e5_4_t make_fp8_e5_4_t(fp8_e5_t x0, fp8_e5_t x1,
+__device__ __forceinline__ fp8_e5_4_t make_fp8_e5_4_t(fp8_e5_t x0, fp8_e5_t x1,

-__forceinline__ __device__ fp8_e5_8_t make_fp8_e5_8_t(fp8_e5_t x0, fp8_e5_t x1,
+__device__ __forceinline__ fp8_e5_8_t make_fp8_e5_8_t(fp8_e5_t x0, fp8_e5_t x1,

-__forceinline__ __device__ fp8_e5_16_t
+__device__ __forceinline__ fp8_e5_16_t

-__forceinline__ __device__ fp8_e5_32_t make_fp8_e5_32_t(
+__device__ __forceinline__ fp8_e5_32_t make_fp8_e5_32_t(
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Actionable comments posted: 0

🧹 Nitpick comments (2)
src/tl_templates/cuda/cuda_fp8.h (2)

79-138: LGTM! FP8 E4 pack functions are correctly implemented.

The pack functions correctly construct FP8 E4 vectors using recursive composition that matches the struct definitions. The logic is sound:

  • Basic 2 and 4-element functions directly assign fields
  • Larger functions (8, 16, 32) recursively compose from smaller packers
  • Parameter ordering (x0-xN, y0-yN) correctly maps to struct fields {x, y}

For consistency with existing code (lines 35, 70), consider swapping the qualifier order:

-__forceinline__ __device__ fp8_e4_2_t make_fp8_e4_2_t(fp8_e4_t x, fp8_e4_t y) {
+__device__ __forceinline__ fp8_e4_2_t make_fp8_e4_2_t(fp8_e4_t x, fp8_e4_t y) {

Apply the same pattern to all new pack functions.


140-199: LGTM! FP8 E5 pack functions mirror the E4 implementation correctly.

The E5 pack functions are correctly implemented with identical structure to the E4 variants, ensuring consistency across both FP8 formats.

Same qualifier order suggestion applies here for consistency with the existing codebase.

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@LeiWang1999 LeiWang1999 merged commit 32ddc1a into tile-ai:main Oct 15, 2025
7 of 8 checks passed
RubiaCx added a commit to RubiaCx/tilelang that referenced this pull request Oct 20, 2025
commit b2acfc3
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Sun Oct 19 22:08:13 2025 +0800

    [Benchmark] Add matmul FP16 benchmark results (tile-ai#1067)

commit 17bd0a6
Author: Tong WU <109033598+Rachmanino@users.noreply.github.com>
Date:   Sun Oct 19 17:34:12 2025 +0800

    [Enhancement] Deprecate split&sum in attn bwd examples on Hopper and migrate to vectorized atomic add (tile-ai#1065)

commit ae9a6f0
Author: Tong WU <109033598+Rachmanino@users.noreply.github.com>
Date:   Sun Oct 19 15:45:58 2025 +0800

    [Refactor][Example] Update linear attention examples and add tests (tile-ai#1010)

    * [Refactor][Example] Update linear attention examples and add tests

    - Refactored the backward and forward linear attention kernels to use shared memory and atomic additions for improved performance.
    - Introduced L2 normalization in the main functions of both examples.
    - Added a new test suite for the linear attention examples to ensure correctness and performance.
    - Updated argument parsing in the main functions for better usability.

    * upd docstring for tma atomic add

    * lint

    * Add flash-linear-attention dependency to requirements.txt

    * Rename main function to chunk_linear_attn_bwd

    * Rename main function to chunk_linear_attn_fwd

    * chore

    ---------

    Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>
    Co-authored-by: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>

commit b7dfdb3
Author: Xuehai Pan <XuehaiPan@pku.edu.cn>
Date:   Sun Oct 19 12:16:41 2025 +0800

    [Misc] Add GitHub issue templates (tile-ai#1057)

commit fb8b3af
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Sun Oct 19 12:15:44 2025 +0800

    [Benchmark] Add H800 SXM Benchmark results (tile-ai#1063)

    * Add document PYTHONPATH build path

    * update fp8 benchmark result

    * remove redpath

    * remove path

    * tflops fix

commit 4ca6c13
Author: Yuqi Dong <134183314+yyttt6@users.noreply.github.com>
Date:   Sun Oct 19 02:43:00 2025 +0800

    [CI]:Reduce test shapes to avoid OOM errors during CI. (tile-ai#1060)

    * [CI]:Reduce test shapes to avoid OOM errors during CI.

    * rabbit

    * Increase number of processes for pytest from 2 to 4

    ---------

    Co-authored-by: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>

commit 759c2e3
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Sun Oct 19 00:35:06 2025 +0800

    [DOC] Add document for develop with PYTHONPATH (tile-ai#1062)

commit bf2de5b
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Sun Oct 19 00:21:59 2025 +0800

    Making version parser more robust against missing or unavailable metadata (tile-ai#1061)

commit 7211164
Author: Chaofan Lin <linchaofan@bytedance.com>
Date:   Fri Oct 17 20:56:01 2025 +0800

    [Refactor] Refactor Pass `LegalizeSafeMemoryAccess` to support recursive load/store rewrite (tile-ai#1050)

    * [Refactor] Refactor Pass  to support recursive load/store rewrite

    * lint

    * recursive collect conds for call_extern

    * fix name

    * [Lint]: [pre-commit.ci] auto fixes [...]

    * lint

    * [Lint]: [pre-commit.ci] auto fixes [...]

    * lint

    * [Lint]: [pre-commit.ci] auto fixes [...]

    * address comment

    * rename pad_value to safe_value

    * lint

    * add oob store test

    * [Lint]: [pre-commit.ci] auto fixes [...]

    * fix

    * fix

    ---------

    Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>

commit 278c0fb
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Fri Oct 17 18:32:43 2025 +0800

    [Enhancement] Introduce a workaround for layout inference for local buffer store (tile-ai#1055)

    * [Enhancement] Improve layout inference for local buffer handling in parallel operations

    * Added logic to check if a loop only manipulates "local" buffers, which affects thread binding decisions.
    * Updated the condition for determining parallel loop execution to account for local buffer stores.
    * Cleaned up comments for clarity and future considerations.

    * [Refactor] Clean up parallel loop condition formatting in layout inference

    * Reformatted the condition for determining parallel loop execution for better readability.
    * Maintained existing logic while enhancing code clarity for future modifications.

    ---------

    Co-authored-by: Zhiwen Mo <zm125@ic.ac.uk>

commit 37b3dbd
Author: LJC00118 <77378439+LJC00118@users.noreply.github.com>
Date:   Fri Oct 17 17:15:59 2025 +0800

    [Enhancement] Improve CUDA compiler detection in CMake (tile-ai#1054)

    * improve CUDA compiler detection in CMake

    * Minor fix

commit 1281d6f
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Fri Oct 17 13:44:08 2025 +0800

    [CI] Disable autofix for pre-commit CI (tile-ai#1053)

commit 35cf888
Author: LJC00118 <77378439+LJC00118@users.noreply.github.com>
Date:   Fri Oct 17 13:43:08 2025 +0800

    [Enhancement] Remove constraint requiring last dimension stride to be 1 (tile-ai#1040)

    * remove last dimension stride must be 1 constraint

    * add vectorize test

    * minor fix

    * [Lint]: [pre-commit.ci] auto fixes [...]

    ---------

    Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>

commit fd1493b
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Fri Oct 17 11:34:35 2025 +0800

    Automatically initialize submodule if missing (tile-ai#1052)

commit cc00fb6
Author: Tong WU <109033598+Rachmanino@users.noreply.github.com>
Date:   Fri Oct 17 11:28:14 2025 +0800

    [Enhancement] Add support for symbolic dimensions in Cython kernel adapter and improve static shape validation in wrapper (tile-ai#1024)

    * [Enhancement] Add support for symbolic dimensions in Cython kernel adapter and improve static shape validation in wrapper

    * [BugFix] Fix shape mismatch and deprecate `T.if()` in fused_moe example

    * [Fix] Add `is_symbolic_expr` function to check for symbolic expressions in TIR

    - Introduced a new utility function `is_symbolic_expr` to determine if an expression is a symbolic expression, enhancing type checking capabilities.
    - Updated shape handling in `CythonKernelAdapter` to utilize the new function, improving handling for symbolic shapes.

commit a79bc5c
Author: Xuehai Pan <XuehaiPan@pku.edu.cn>
Date:   Thu Oct 16 20:38:23 2025 +0800

    [CI] Fix ROCm CI (tile-ai#1043)

    * [CI] fix ROCm CI

    * feat: add a hook to error out on no test runs

commit 1f4ffdb
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Thu Oct 16 17:53:45 2025 +0800

    [Bugfix] Improves compatibility when checking for MPS availability in different PyTorch builds. (tile-ai#1051)

commit e3742d3
Author: Yichen Yan <wenji.yyc@alibaba-inc.com>
Date:   Thu Oct 16 15:52:10 2025 +0800

    Allow mma gemm for all cuda (tile-ai#1047)

commit 0ff4f42
Author: Yuqi Dong <134183314+yyttt6@users.noreply.github.com>
Date:   Thu Oct 16 12:41:09 2025 +0800

    [Feature]: Add test for atomicadd auto vectorize and remove useless code (tile-ai#1019)

    * update

    * format

    * rabbit

commit bd1c7b3
Author: Yu Cheng <54519279+chengyupku@users.noreply.github.com>
Date:   Thu Oct 16 02:52:35 2025 +0800

    [Refactor] Use `has_simt_copy` to decide whether to insert `set_max_nreg` (tile-ai#982)

commit 8f001e0
Author: Tong WU <109033598+Rachmanino@users.noreply.github.com>
Date:   Thu Oct 16 01:10:28 2025 +0800

    [BugFix] Phaseout dependency of Triton in sink examples to make CI happy (tile-ai#1045)

    * [BugFix] Phaseout dependency of Triton in sink examples to make CI happy

    - Added `benchmark_gqa_sink_fwd.py` and `benchmark_mha_sink_fwd.py` to evaluate performance of GQA and MHA attention mechanisms using Triton.
    - Refactored existing attention sink implementations to remove Triton kernel definitions from the reference programs, streamlining the code.
    - Updated input generation and benchmarking logic to enhance configurability and performance measurement.
    - Improved overall structure and organization of the examples for better clarity and usability.

    * [Lint]: [pre-commit.ci] auto fixes [...]

    ---------

    Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>

commit 8ce2778
Author: Xuehai Pan <XuehaiPan@pku.edu.cn>
Date:   Wed Oct 15 22:12:41 2025 +0800

    [CI][Refactor] Merge test CI workflow files into one (tile-ai#973)

    * refactor: merge test CI workflow files into one

    * chore: set `UV_INDEX_STRATEGY=unsafe-best-match`

    * feat: add AST test with Python 3.8

    * feat: implement manual caching mechanism for self-hosted runners

    * refactor: simplify cache logic for self-hosted runners

    * chore: clear uv cache on failure

    * chore: print format.sh output to logs

    * chore: improve uv caching

    * chore: disable parallel test

    * chore: use `PYTHONDEVMODE=1` in CI

    * feat: enable coredump generation

    * fix: fix perfbench condition

    * Revert "feat: enable coredump generation"

    This reverts commit c52da65.

    * chore: move example CI down

    * Revert "chore: move example CI down"

    This reverts commit 9d8e650.

    * chore: skip example `test_example_mha_sink_bwd_bhsd`

    * chore: skip example `test_example_gqa_sink_bwd_bhsd`

    * fix: fix example argument passing

    * fix: loosen test criteria

    * chore: rename `CMAKE_CONFIGURE_OPTIONS` -> `CLANG_TIDY_CMAKE_OPTIONS` for clarity

    * feat: enable parallel testings

    * chore: update pytest options

    * remove skipped test as now been resolved

    * chore: empty commit to re-trigger ci

    * test for n 1

    * chore: remove ` --numprocesses=1` option in example

    * chore: disable failfast

    * chore: update cibw selection

    * fix: fix git submodule clone

    * chore: update cibw commands

    * fix: fix yapf multiprocessing

    * chore: setup ccache for CIBW on macOS only

    * chore: update comments

    * chore: update artifact listing

    * fix: do not fail if not found nvcc in PATH

    * fix: fix flash-attn installation

    * chore: update dist workflow trigger

    * chore: remove outdated comments

    * chore(workflows/dist): simplify build matrix strategy

    * fix: fix CUDA path finding

    * fix: fix CUDA path finding

    * chore: imcrease CI timeout

    * ci: disable failfast

    * fix: hide path prefix

    * chore: more verbose

    * chore: disable PR trigger for dist workflow

    * fix: seed for tests

    * fix: use nightly torch for ROCm tests

    * chore: enable PR trigger for dist workflow

    * chore: stop uploading debug wheels as artifacts in PR

    * chore: do not run workflows in forks

    * chore: housekeep requirements

    * chore: use Nightly-ROCm-6.3 for CI

    * chore: use Nightly-ROCm-6.4 for CI

    * Update ROCm toolkit version to 7.0

    * chore: restore previous rocm-ci.yml for test

    * fix: cleanup PYTHONPATH

    * chore: remove previous rocm-ci.yml

    * ci fix

    * chore: remove previous rocm-ci.yml

    * chore: enable parallel example run

    ---------

    Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>
    Co-authored-by: alex_xiao <xinyuxiao2024@gmail.com>

commit 80665cd
Author: alex_xiao <xinyuxiao2024@gmail.com>
Date:   Wed Oct 15 21:17:14 2025 +0800

    fix bug&add amd examples (tile-ai#966)

    * [Enhancement] Refactor buffer index handling for improved precision and clarity (tile-ai#668)

    - Enhanced buffer index handling to address precision issues by removing redundant operations.
    - Streamlined the logic for determining buffer overlaps, ensuring more accurate conflict detection.
    - Updated related documentation to reflect changes in buffer management practices.

    * Remove obsolete test script for AMD example, streamlining the examples directory.

    * Remove unused dtype_size variable in AMD example script to streamline code.

    * Add input configuration file and update AMD example script for enhanced flexibility

    - Introduced a new input.txt file for configurable parameters.
    - Modified the example_amd_flash_attn_fwd.py script to allow for a wider range of configurations, including additional options for num_stages, enable_rasterization, and k_pack.
    - Streamlined the main function for better clarity and organization.
    - Added a new test script to facilitate running the example with specified parameters.

    * Remove input configuration file and obsolete test script; enhance AMD example with swizzle layout annotations

    - Deleted input.txt and test.sh files as they are no longer needed.
    - Updated example_amd_flash_attn_fwd.py to include swizzle layout annotations for shared memory, improving bank conflict avoidance.
    - Reintroduced swizzle usage in the kernel for better performance.

    * Refactor AMD example script for FlashAttention-2

    - Updated function names for clarity, changing `get_v2_configs` to `get_configs` and `fast_flashattn_v2` to `fast_flashattn`.
    - Streamlined the main function by renaming `main_v2` to `main` and adjusting the corresponding calls.
    - Removed outdated comments and improved code organization for better readability.

    * Refactor formatting in AMD FlashAttention example script

    - Improved code readability by adjusting line breaks and indentation in the `fast_flashattn` function.
    - Streamlined the `main` function parameter formatting for consistency.
    - Removed unnecessary blank lines to enhance overall code organization.

    * Update example_amd_flash_attn_fwd.py

    * Enhance AMD example script and update CI workflows

    - Improved the `example_amd_flash_attn_fwd.py` script for better clarity and organization.
    - Added new CI workflows for AMD and documentation publishing.
    - Updated various requirements files to include necessary dependencies.
    - Introduced new test cases and examples for better coverage and functionality.
    - Refactored existing code for improved readability and maintainability.

    * Remove redundant tool cache cleanup step in AMD CI workflow

    * Remove `torch` dependency from `requirements-rocm.txt` to streamline requirements.

    * Add new AMD FlashAttention example and test script

    - Introduced `example_amd_flash_attn_bwd.py` for backward attention computation using TileLang.
    - Added `test.sh` script to facilitate running the new example with specified parameters.
    - Enhanced the overall structure and organization of the example for better clarity and usability.

    * Update configurations in `example_amd_flash_attn_fwd.py` for autotuner

    - Reduced the number of threads and `num_split_q` options for improved performance.
    - Adjusted `panel_size` options to streamline configuration settings.

    * Update submodule 'tvm' to commit 6ccc74f622c7ec4ac25d430d0f6546e7b9edb217

    * Update submodule 'tvm' to commit 14ff70ab142b9e5a31bbf9c7923c8a697d41e86c

    * Add example for AMD Flash Attention backward pass implementation

    - Introduced a new example script `example_amd_flash_attn_bwd.py` demonstrating the forward and backward operations of Flash Attention using TileLang.
    - Implemented JIT-compiled functions for both forward and backward passes, including preprocessing and postprocessing steps.
    - Added a main function to facilitate testing and benchmarking of the attention mechanism with configurable parameters.
    - Included reference implementation for validation against PyTorch's attention mechanism.

    This addition enhances the examples directory by providing a comprehensive guide for users to understand and utilize Flash Attention in their applications.

    * Enhance AMD Flash Attention example with additional testing capabilities

    - Updated `example_amd_flash_attn_bwd.py` to include more comprehensive testing features for the Flash Attention implementation.
    - Improved the main function to allow for better parameter configuration and benchmarking.
    - Added validation checks against PyTorch's attention mechanism to ensure accuracy and reliability of the example.

    This update aims to provide users with a more robust tool for understanding and utilizing Flash Attention in their applications.

    * Update submodule TVM to commit a64a5926a6e59f5417ef2501f9d88b467337cf6a

    * Refactor HIP intrinsic rules to CUDA

    - Updated file name from `intrin_rule_hip.cc` to `intrin_rule_cuda.cc` to reflect the change in focus from HIP to CUDA intrinsic rules.
    - Adjusted include paths for better organization and clarity in the code structure.

    * Update AMD CI workflow to uninstall specific PyTorch packages before installation

    - Removed the installation of `flash_attn==2.5.8` to streamline the CI process.
    - Added a step to uninstall `torch`, `torchvision`, and `torchaudio` prior to installing pre-release versions, ensuring compatibility and reducing potential conflicts.

    * Remove unused shared memory allocations in AMD Flash Attention backward example

    - Eliminated the allocation of shared memory for `dv_shared` and `dk_shared` in `example_amd_flash_attn_bwd.py` to streamline memory usage and improve performance.
    - This change focuses on optimizing the backward pass implementation by reducing unnecessary memory overhead.

    * Remove unnecessary pip uninstall command from AMD CI workflow

    - Eliminated the step to uninstall `torch`, `torchvision`, and `torchaudio` in the AMD CI workflow, as it is no longer required for the installation of pre-release versions.
    - This change simplifies the CI process and reduces potential overhead during package management.

    * Refactor DispatchHIPWarpActiveMask function in HIP intrinsic rules

    - Updated the return statement to use std::string for concatenation in the case of 16-bit types, improving code clarity.
    - Added a null check for the CallNode pointer in DispatchHIPWarpActiveMask to enhance robustness and prevent potential dereferencing issues.

    * Refactor formatting of HIP intrinsic rule registrations

    - Adjusted the formatting of TVM_REGISTER_OP calls for better readability by aligning method chaining.
    - No functional changes were made; this update focuses on code style improvements to enhance maintainability.

    * Update file name and documentation for HIP intrinsic rules

    - Renamed the file from `intrin_rule_cuda.cc` to `intrin_rule_hip.cc` to accurately reflect the focus on HIP intrinsic rules.
    - Updated the file documentation to clarify its purpose as related to HIP rather than CUDA.

    * Enhance DispatchHIPShuffle function with clang-analyzer comments

    - Added NOLINTBEGIN and NOLINTEND comments to the DispatchHIPShuffle function to suppress clang-analyzer warnings related to inner pointer usage.
    - This change improves code clarity and maintains compliance with static analysis tools.

    * lint fix

    * fix

    * Enhance autotuner configurations in example_amd_flash_attn_fwd.py by adding new block sizes, stages, and panel sizes. Update test script to use relative Python path and adjust parameters for consistency.

    * Add backward attention example to test script

    - Extended the test.sh script to include a new backward attention example using example_amd_flash_attn_bwd.py.
    - Added parameters for batch size, context length, and head dimensions to ensure consistency with the forward example.
    - Updated the command for the backward tile example to match the new configuration.

    * Refactor FlashAttention implementation in example_amd_flash_attn_bwd.py and example_amd_flash_attn_fwd.py

    - Introduced new functions for forward and backward configurations to enhance autotuning capabilities.
    - Updated the FlashAttention forward and backward functions to improve performance and maintainability.
    - Adjusted test script parameters for consistency and clarity, including the addition of group handling.
    - Enhanced the autotuner configurations by refining block sizes and stages for better performance tuning.
    - Updated the main function to reflect changes in parameter names and types for better usability.

    * Enhance FlashAttention backward implementation in example_amd_flash_attn_bwd.py

    - Updated the backward function to return additional outputs, including log-sum-exp (LSE) values for improved gradient calculations.
    - Refined autotuner configurations by adding new block sizes and adjusting parameters for better performance tuning.
    - Improved shared memory usage in the backward pass to optimize memory access patterns and enhance computational efficiency.
    - Updated the main function to reflect changes in parameter handling and ensure consistency with the forward pass.
    - Enhanced correctness checks in the main function to include LSE validation alongside gradient checks.

    * Enhance FlashAttention backward implementation in example_amd_flash_attn_bwd.py

    - Introduced a scaling factor for improved numerical stability in gradient calculations.
    - Optimized shared memory usage by adding new shared buffers for intermediate calculations.
    - Refined the handling of tensor fragments to improve performance and maintainability.
    - Updated the main function to ensure compatibility with the new output parameters for backward operations.
    - Removed unnecessary parameters from the test script to streamline execution.

    * Refactor FlashAttention implementation in example_amd_flash_attn_bwd.py and example_mha_bwd.py

    - Updated the forward and backward functions to improve numerical stability and performance.
    - Enhanced shared memory usage by optimizing buffer allocations and reducing unnecessary parameters.
    - Adjusted autotuner configurations for better performance tuning and compatibility with new output parameters.
    - Added debugging and benchmarking functions for improved correctness verification and performance analysis.
    - Updated the main function to reflect changes in parameter handling and ensure consistency across examples.

    * Enhance FlashAttention backward implementation in example_amd_flash_attn_bwd.py

    - Updated scaling factor application for improved numerical stability in gradient calculations.
    - Refined tensor handling to ensure consistency with forward pass operations.
    - Optimized atomic operations for writing gradients to dK and dV using fp32 for better precision.
    - Adjusted comments for clarity and alignment with standard implementation practices.

    * Expand autotuner configurations in example_amd_flash_attn_bwd.py and update test.sh

    - Increased the range of block sizes and stages for forward and backward configurations to enhance performance tuning.
    - Adjusted the test script to include additional parameters for batch size and head dimensions, ensuring consistency with the forward example.
    - Improved comments for clarity and alignment with the updated configurations.

    * Enhance performance calculations and benchmarking in example_amd_flash_attn_bwd.py

    - Updated FLOPs calculation to account for both forward and backward passes, clarifying the total computational cost.
    - Modified benchmarking functions to evaluate the complete forward and backward performance of both reference and Tile-lang implementations.
    - Improved comments for better understanding of the performance metrics and implementation details.
    - Removed unnecessary parameter from test.sh to streamline execution.

    * Remove forward attention test commands from test.sh and retain backward attention execution for streamlined testing.

    * Refactor FlashAttention forward and backward implementations in example_amd_flash_attn_bwd.py and example_amd_flash_attn_fwd.py

    - Updated the forward function to return both output and log-sum-exp (LSE) values for improved gradient calculations.
    - Enhanced autotuner configurations for forward pass, including new parameters for better performance tuning.
    - Refined scaling factor calculations for numerical stability in both forward and backward passes.
    - Improved comments and documentation for clarity and consistency across implementations.
    - Adjusted main function to reflect changes in parameter handling and ensure compatibility with new output requirements.

    * Refactor FlashAttention implementation in example_amd_flash_attn_bwd.py

    - Removed outdated comments and improved clarity in the code.
    - Enhanced the forward function to consistently return output and log-sum-exp (LSE) values.
    - Updated autotuner configurations to include new parameters for better performance tuning.
    - Refined tensor handling and scaling factor calculations for improved numerical stability.
    - Adjusted the main function to ensure compatibility with updated output requirements and parameter handling.

    * Enhance FlashAttention backward implementation in example_amd_flash_attn_bwd.py

    - Updated configuration parameters for backward calculations, including new options for block sizes, threads, and rasterization.
    - Added new parameters (k_pack, qk_coalesced_width, v_coalesced_width) to improve performance tuning and memory access patterns.
    - Modified tensor copy operations to utilize coalesced widths for optimized memory loads.
    - Enhanced GEMM operations with k_pack for improved computational efficiency.
    - Refined the configuration generation logic to accommodate the new parameters, ensuring comprehensive coverage for backward pass scenarios.

    * Refactor configuration and tensor operations in example_amd_flash_attn_bwd.py

    - Updated backward configuration parameters to include larger block sizes and a wider range of threads for enhanced performance tuning.
    - Removed unnecessary parameters (k_pack, qk_coalesced_width, v_coalesced_width) from function signatures and tensor operations to simplify the implementation.
    - Optimized tensor copy operations by eliminating coalesced width specifications, streamlining memory access patterns.
    - Adjusted GEMM operations to improve computational efficiency without the use of k_pack.

    * Enhance HIP code generation and FP8 type support

    - Added support for additional FP8 types (e4m3, e4m3b11fnuz, e5m2fnuz, e8m0) in codegen_hip.cc to improve compatibility.
    - Updated error logging to include unsupported FP8 type details for better debugging.
    - Implemented handling for loop break and no-op register management in HIP within VisitExpr_ method.
    - Introduced new FP8 vector types (e5 and e8) in hip_fp8.h for enhanced functionality.
    - Added overloads for AtomicAdd in common.h to support both pointer and value arguments.

    * Enhance FP8 type support and clarify accumulator handling in HIP

    - Expanded FP8 type support in codegen_hip.cc to include additional float8 formats.
    - Updated gemm.h to clarify the handling of the accumulator when clear_accum is true.
    - Added comments in hip_fp8.h to indicate that E8M0 types are not supported in the current HIP version.

    * Remove deprecated files and update print statements for clarity in example_amd_flash_attn_bwd.py

    * Update print statement formatting for clarity in example_amd_flash_attn_bwd.py

    * Remove redundant verification results summary print statement in example_amd_flash_attn_bwd.py for cleaner output.

    * Fix formatting inconsistencies in example_amd_flash_attn_bwd.py and example_amd_flash_attn_fwd.py by adding spaces for improved readability in configuration parameters and print statements.

    * Refactor and enhance HIP code generation for improved FP8 support

    - Reorganized and cleaned up code in codegen_hip.cc for better readability and maintainability.
    - Enhanced handling of FP8 types, including additional formats and improved error logging for unsupported types.
    - Updated AtomicAdd function in common.h to streamline its implementation.
    - Refined the PrintVecElemLoadExpr method to handle volatile loads more effectively.
    - Added function to manage the addition of new functions in the code generation process.

    * Fix formatting issue in HIP code generation for MFMA call

    - Adjusted the indentation of the MFMA call code block in codegen_hip.cc for improved readability and consistency.

    * Refactor HIP code generation and enhance FP8 type handling

    - Reintroduced necessary includes and reorganized code in codegen_hip.cc for improved structure and readability.
    - Enhanced the GetFP8Type function to support additional FP8 formats and improved error handling for unsupported types.
    - Updated PrintType and PrintVecElemLoadExpr methods to better manage type conversions and vector element loading.
    - Refined the AddFunction method to streamline function addition in the code generation process.

    * Remove unnecessary blank line in example_amd_flash_attn_bwd.py for improved code cleanliness.

    * Refactor backward attention implementation in example_amd_flash_attn_bwd.py

    - Updated the GEMM operation to use shared memory for improved performance.
    - Adjusted parallelization parameters to enhance efficiency in the backward pass.

    * Fix formatting by removing an unnecessary blank line in example_amd_flash_attn_bwd.py for improved code cleanliness.

    * Add additional test cases for `assert_tl_matmul_correctness` with `float8_e4m3fnuz` and various configurations

    * Refactor test case formatting for `assert_tl_matmul_correctness` in `test_tilelang_gemm_mfma_intrinsic.py`

    ---------

    Co-authored-by: xinxyxiao <xinyxiao@amd.com>
    Co-authored-by: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
    Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>

commit b78d840
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Wed Oct 15 16:38:55 2025 +0800

    [Language] Expose `T.get_warp_idx_sync` and `T.shuffle_elect` for efficient thread election (tile-ai#989)

    * Expose CUDA warp/lane intrinsics in TileLang frontend

    * generalize warp indexing intrinsics and add coverage

    * [Lint]: [pre-commit.ci] auto fixes [...]

    ---------

    Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>

commit 32ddc1a
Author: LJC00118 <77378439+LJC00118@users.noreply.github.com>
Date:   Wed Oct 15 15:25:43 2025 +0800

    [CUDA] Add pack functions for FP8 types (tile-ai#967)

    * Remove an incorrect check

    * add fp8 pack function

    * code lint

    * minor fix

    * minor fix

    * minor fix

    * Minor fix

    * Minor fix

commit c67f73b
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Wed Oct 15 15:12:08 2025 +0800

    [Env] Optimize the mechanism for locating `TL_LIBS` (tile-ai#1038)

commit e539952
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Wed Oct 15 15:11:40 2025 +0800

    [TIR] Revert some changes of Pass `LowerIntrin` (tile-ai#1035)

    * keep >> instead of /

    * re think replicate

    * lint fix

    * handle const int buffers

    * rep fix

    ---------

    Co-authored-by: Zhiwen Mo <zm125@ic.ac.uk>

commit 5767475
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Tue Oct 14 23:55:27 2025 +0800

    [CI] Disable buggy(maybe) warp specialized kernel ci test for H20 (tile-ai#1033)

commit eed320f
Author: Lei Wang <34334180+LeiWang1999@users.noreply.github.com>
Date:   Tue Oct 14 21:51:31 2025 +0800

    [Bugfix] Recover code for flexible parallel (tile-ai#1032)

    * recover flex parallel process

    * lint fix

    ---------

    Co-authored-by: Zhiwen Mo <zm125@ic.ac.uk>

commit 1e8f0b1
Author: Tong WU <109033598+Rachmanino@users.noreply.github.com>
Date:   Tue Oct 14 17:26:23 2025 +0800

    [Enhancement] Update abs function for half_t and bfloat_t to use cutlass implementation (tile-ai#1023)

    * [Enhancement] Update abs function for half_t and bfloat_t to use cutlass implementation

    * [Lint]: [pre-commit.ci] auto fixes [...]

    * optimize amd ci

    ---------

    Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
    Co-authored-by: LeiWang1999 <leiwang1999@outlook.com>
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