LVS check failed!

[Flians]

Hello, I used your gf180mcuD configuration to synthesize standard cells and always got the error "LVS check failed!". Could you please help me check it? Thank you. One spice netlist is as follows:

.subckt GF180MCU_FD_SC_MCU9T5V0__OR3_1 VDD GND A3 A2 A1 Z
M0 VSS A1 Z_NEG GND nmos w=1.83u l=0.5u
M1 Z_NEG A2 VSS GND nmos w=1.83u l=0.5u
M2 VSS A3 Z_NEG GND nmos w=1.83u l=0.5u
M3 Z Z_NEG VSS GND nmos w=1.83u l=0.5u
M4 NET_0 A1 Z_NEG VDD pmos w=1.32u l=0.6u
M5 NET_1 A2 NET_0 VDD pmos w=1.32u l=0.6u
M6 NET_1 A3 VDD VDD pmos w=1.32u l=0.6u
M7 Z Z_NEG VDD VDD pmos w=1.32u l=0.6u
.ends GF180MCU_FD_SC_MCU9T5V0__OR3_1

[thesourcerer8]

I am sorry for my late reply. I often saw LVS check errors from lclayout which seemed to be wrong to me. I think that most likely the LVS checker in lclayout should be improved.