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Require a memory and writeback stage for the CFU plugin. #2

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Merged
merged 1 commit into from
Aug 2, 2021
Merged

Require a memory and writeback stage for the CFU plugin. #2

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4 changes: 2 additions & 2 deletions pythondata_cpu_vexriscv/verilog/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -27,10 +27,10 @@ VexRiscv_MinDebug.v: $(SRC)
sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 0 --dCacheSize 0 --mulDiv false --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_MinDebug"

VexRiscv_Fomu.v: $(SRC)
sbt compile "runMain vexriscv.GenCoreDefault --safe false --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --memoryAndWritebackStage false --outputFile VexRiscv_Fomu"
sbt compile "runMain vexriscv.GenCoreDefault --safe false --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --outputFile VexRiscv_Fomu"

VexRiscv_FomuCfu.v: $(SRC)
sbt compile "runMain vexriscv.GenCoreDefault --safe false --cfu true --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --memoryAndWritebackStage false --outputFile VexRiscv_FomuCfu"
sbt compile "runMain vexriscv.GenCoreDefault --safe false --cfu true --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --outputFile VexRiscv_FomuCfu"

VexRiscv_Full.v: $(SRC)
sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --outputFile VexRiscv_Full"
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