soc: RT600: Update the core speed

1. Code for the power mananagement is available in source format 2. Increase the core speed to 250MHz. Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
tbursztyka · Nov 13, 2020 · 2574611 · 2574611
1 parent 4b93fdb
commit 2574611
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Showing 3 changed files with 37 additions and 32 deletions.
diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.soc b/soc/arm/nxp_imx/rt6xx/Kconfig.soc
@@ -52,6 +52,18 @@ config INIT_SYS_PLL
 config INIT_AUDIO_PLL
 	bool "Initialize Audio PLL"
 
+config XTAL_SYS_CLK_HZ
+	int "External oscillator frequency"
+	help
+	  Set the external oscillator frequency in Hz. This should be set by the
+	  board's defconfig.
+
+config SYSOSC_SETTLING_US
+	int "System oscillator settling time"
+	help
+	  Set the board system oscillator settling time in us. This should be set by the
+	  board's defconfig.
+
 menuconfig NXP_IMX_RT6XX_BOOT_HEADER
 	bool "Enable the boot header"
 	help

diff --git a/soc/arm/nxp_imx/rt6xx/soc.c b/soc/arm/nxp_imx/rt6xx/soc.c
@@ -106,31 +106,22 @@ static ALWAYS_INLINE void clock_init(void)
 {
 #ifdef CONFIG_SOC_MIMXRT685S_CM33
 	/* Configure LPOSC clock*/
-	if ((SYSCTL0->PDRUNCFG0 & SYSCTL0_PDRUNCFG0_LPOSC_PD_MASK) != 0) {
-		POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
-	}
-
+	POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
 	/* Configure FFRO clock */
-	if ((SYSCTL0->PDRUNCFG0 & SYSCTL0_PDRUNCFG0_FFRO_PD_MASK) != 0) {
-		POWER_DisablePD(kPDRUNCFG_PD_FFRO);
-		CLOCK_EnableFfroClk(kCLOCK_Ffro48M);
-	}
-	if ((SYSCTL0->PDRUNCFG0 & SYSCTL0_PDRUNCFG0_SFRO_PD_MASK) != 0) {
-		/* Configure SFRO clock */
-		POWER_DisablePD(kPDRUNCFG_PD_SFRO);
-		CLOCK_EnableSfroClk();
-	}
+	POWER_DisablePD(kPDRUNCFG_PD_FFRO);
+	CLOCK_EnableFfroClk(kCLOCK_Ffro48M);
+	/* Configure SFRO clock */
+	POWER_DisablePD(kPDRUNCFG_PD_SFRO);
+	CLOCK_EnableSfroClk();
 
-	if ((SYSCTL0->PDRUNCFG0 & SYSCTL0_PDRUNCFG0_SYSXTAL_PD_MASK) != 0) {
-		/* Configure SYSOSC clock source */
-		POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
-		CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US);
-	}
-	CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ);
-
-	/* Let CPU and AHB bus run on FFRO 48MHz for safe switching. */
+	/* Let CPU run on FFRO for safe switching. */
 	CLOCK_AttachClk(kFFRO_to_MAIN_CLK);
-	CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U);
+
+	/* Configure SYSOSC clock source */
+	POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
+	POWER_UpdateOscSettlingTime(CONFIG_SYSOSC_SETTLING_US);
+	CLOCK_EnableSysOscClk(true, true, CONFIG_SYSOSC_SETTLING_US);
+	CLOCK_SetXtalFreq(CONFIG_XTAL_SYS_CLK_HZ);
 
 #ifdef CONFIG_INIT_SYS_PLL
 	/* Configure SysPLL0 clock source */
@@ -139,16 +130,25 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
 #endif
 
-	/* Set FRGPLLCLKDIV divider to value 12 */
-	CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U);
-
 #ifdef CONFIG_INIT_AUDIO_PLL
 	/* Configure Audio PLL clock source */
 	CLOCK_InitAudioPll(&g_audioPllConfig);
 	CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26);
 	CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U);
 #endif
 
+	/* Set SYSCPUAHBCLKDIV divider to value 2 */
+	CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U);
+
+	/* Set up clock selectors - Attach clocks to the peripheries */
+	CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK);
+
+	/* Set up dividers */
+	/* Set PFC0DIV divider to value 2 */
+	CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U);
+	/* Set FRGPLLCLKDIV divider to value 12 */
+	CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U);
+
 	CLOCK_AttachClk(kSFRO_to_FLEXCOMM0);
 
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay)

diff --git a/soc/arm/nxp_imx/rt6xx/soc.h b/soc/arm/nxp_imx/rt6xx/soc.h
@@ -24,13 +24,6 @@
 
 #endif /* !_ASMLANGUAGE */
 
-/*!< Board System oscillator settling time in us */
-#define BOARD_SYSOSC_SETTLING_US 260U
-/*!< Board xtal32K frequency in Hz */
-#define BOARD_XTAL32K_CLK_HZ 32768U
-/*!< Board xtal frequency in Hz */
-#define BOARD_XTAL_SYS_CLK_HZ 24000000U
-
 /*!<@brief Analog mux is disabled */
 #define IOPCTL_PIO_ANAMUX_DI 0x00u
 /*!<@brief Analog mux is enabled */