patch: add support dp_memory for tang primer 20k board

src/includes/scr1_arch_description.svh

@@ -46,6 +46,7 @@
 // `define SCR1_TRGT_FPGA_INTEL_ARRIAV  // target platform is Intel Arria V FPGAs (used in the SCR1-SDK project)
 // `define SCR1_TRGT_FPGA_XILINX        // target platform is Xilinx FPGAs (used in the SCR1-SDK project)
 // `define SCR1_TRGT_ASIC               // target platform is ASIC
+// `define SCR1_TRGT_FPGA_GOWIN         // target platform is Gowin FPGAs (used in the SCR1-SDK project)
 // `define SCR1_TRGT_SIMULATION         // target is simulation (enable simulation code)
 
  `include "scr1_arch_custom.svh"

src/top/scr1_dp_memory.sv

@@ -65,6 +65,102 @@ always_ff @(posedge clk) begin
     qa <= memory_array[addra];
 end
 
+`elsif SCR1_TRGT_FPGA_GOWIN
+
+`include "gowin_dpb.v"
+localparam int unsigned RAM_SIZE_WORDS = SCR1_SIZE/SCR1_NBYTES;
+logic [3:0] wenbb;
+assign wenbb = {4{wenb}} & webb;
+
+logic [7:0] douta1;
+logic [7:0] douta2;
+logic [7:0] douta3;
+logic [7:0] douta4;
+
+logic [7:0] doutb1;
+logic [7:0] doutb2;
+logic [7:0] doutb3;
+logic [7:0] doutb4;
+
+assign qa = {douta4, douta3, douta2, douta1};
+assign qb = {doutb4, doutb3, doutb2, doutb1};
+
+Gowin_DPB dpb1(
+        .douta(douta1), //output [7:0] douta
+        .doutb(doutb1), //output [7:0] doutb
+        .clka(clk), //input clka
+        .ocea(), //input ocea
+        .cea('1), //input cea
+        .reseta(), //input reseta
+        .wrea(), //input wrea
+        .clkb(clk), //input clkb
+        .oceb(), //input oceb
+        .ceb('1), //input ceb
+        .resetb(), //input resetb
+        .wreb(wenbb[0]), //input wreb
+        .ada(addra), //input [15:0] ada
+        .dina(), //input [7:0] dina
+        .adb(addrb), //input [15:0] adb
+        .dinb(datab[0+:8]) //input [7:0] dinb
+    );
+
+Gowin_DPB dpb2(
+        .douta(douta2), //output [7:0] douta
+        .doutb(doutb2), //output [7:0] doutb
+        .clka(clk), //input clka
+        .ocea(), //input ocea
+        .cea('1), //input cea
+        .reseta(), //input reseta
+        .wrea(), //input wrea
+        .clkb(clk), //input clkb
+        .oceb(), //input oceb
+        .ceb('1), //input ceb
+        .resetb(), //input resetb
+        .wreb(wenbb[1]), //input wreb
+        .ada(addra), //input [15:0] ada
+        .dina(), //input [7:0] dina
+        .adb(addrb), //input [15:0] adb
+        .dinb(datab[8+:8]) //input [7:0] dinb
+    );
+
+Gowin_DPB dpb3(
+        .douta(douta3), //output [7:0] douta
+        .doutb(doutb3), //output [7:0] doutb
+        .clka(clk), //input clka
+        .ocea(), //input ocea
+        .cea('1), //input cea
+        .reseta(), //input reseta
+        .wrea(), //input wrea
+        .clkb(clk), //input clkb
+        .oceb(), //input oceb
+        .ceb('1), //input ceb
+        .resetb(), //input resetb
+        .wreb(wenbb[2]), //input wreb
+        .ada(addra), //input [15:0] ada
+        .dina(), //input [7:0] dina
+        .adb(addrb), //input [15:0] adb
+        .dinb(datab[16+:8]) //input [7:0] dinb
+    );
+
+Gowin_DPB dpb4(
+        .douta(douta4), //output [7:0] douta
+        .doutb(doutb4), //output [7:0] doutb
+        .clka(clk), //input clka
+        .ocea(), //input ocea
+        .cea('1), //input cea
+        .reseta(), //input reseta
+        .wrea(), //input wrea
+        .clkb(clk), //input clkb
+        .oceb(), //input oceb
+        .ceb('1), //input ceb
+        .resetb(), //input resetb
+        .wreb(wenbb[3]), //input wreb
+        .ada(addra), //input [15:0] ada
+        .dina(), //input [7:0] dina
+        .adb(addrb), //input [15:0] adb
+        .dinb(datab[24+:8]) //input [7:0] dinb
+    );
+
 `else // SCR1_TRGT_FPGA_INTEL
 
 // CASE: OTHERS - SCR1_TRGT_FPGA_XILINX, SIMULATION, ASIC etc

src/top/scr1_top_ahb.sv

@@ -94,7 +94,7 @@ logic                                               rst_n_sync;
 logic                                               cpu_rst_n_sync;
 logic                                               core_rst_n_local;
 `ifdef SCR1_DBG_EN
-logic                                               tapc_trst_n;
+logic                                               tapc_trst_n/* synthesis syn_keep = 1 */;
 `endif // SCR1_DBG_EN
 
 // Instruction memory interface from core to router