customizable top module name, audio wav output in verilator framework…

… (wip)

bin/silice-make.py

@@ -43,7 +43,8 @@ def colored(str,clr,attrs=0):
 parser.add_argument('-l','--list_boards', help="List all available target boards.", action="store_true")
 parser.add_argument('-r','--root', help="Root directory, use to override default frameworks.")
 parser.add_argument('-D','--defines', help="List of comma-separated defines to pass to Silice, e.g. -D A=0,B=1")
-parser.add_argument('-a','--args', help="List of comma-separated additional command line parameter to pass to Silice, e.g. -a force-reset-init")
+parser.add_argument('-a','--args', help="List of comma-separated additional command line switches to pass to Silice, e.g. -a force-reset-init")
+parser.add_argument('--top', help="Name of the top module (default: top).",  default="top")
 parser.add_argument('--no_build', help="Only generate verilog output file.", action="store_true")
 parser.add_argument('--no_program', help="Only generate verilog output file and build bitstream.", action="store_true")
 parser.add_argument('--reprogram', help="Only program device.", action="store_true")
@@ -280,6 +281,8 @@ def colored(str,clr,attrs=0):
     if args.defines:
         for define in args.defines.split(','):
             defines = defines + " -D " + define
+    # top module name
+    os.environ["SILICE_TOP"] = args.top
     # additional command line parameters
     add_args = ""
     if args.args:
@@ -290,9 +293,9 @@ def colored(str,clr,attrs=0):
     print('launching command     ', colored(command,'cyan'))
     if platform.system() == "Windows":
         bash = "env bash"
-        os.system(bash + " " + command + " " + defines + " " + add_args)
+        os.system(bash + " " + command + " " + defines + " " + add_args + " --top " + args.top)
     else:
-        os.system(command + " " + defines + " " + add_args)
+        os.system(command + " " + defines + " " + add_args + " --top " + args.top)
 
 elif target_builder['builder'] == 'edalize':
 
@@ -364,6 +367,8 @@ def colored(str,clr,attrs=0):
         if args.args:
             for arg in args.args.split(','):
                 cmd.append("--" + arg)
+        # top module name
+        cmd.append("--top " + args.top)
         # launch
         try:
             subprocess.check_call(cmd, cwd=out_dir, env=my_env, stdin=subprocess.PIPE)

frameworks/boards/tinytapeout/tinytapeout.sh

@@ -18,6 +18,7 @@ echo "build script: BUILD_DIR      = $BUILD_DIR"
 echo "build script: BOARD_DIR      = $BOARD_DIR"
 echo "build script: FRAMEWORKS_DIR = $FRAMEWORKS_DIR"
 echo "build script: FRAMEWORK_FILE = $FRAMEWORK_FILE"
+echo "build script: SILICE_TOP     = $SILICE_TOP"
 
 export PATH=$PATH:$SILICE_DIR/../tools/fpga-binutils/mingw64/bin/:$SILICE_DIR
 case "$(uname -s)" in
@@ -43,7 +44,7 @@ if [[ ! -z "${NO_BUILD}" ]]; then
   exit
 fi
 
-yosys -l yosys.log -p "read_verilog -sv build.v" -p 'synth_ice40 -relut -top tt_um_silice -json build.json'
+yosys -l yosys.log -p "read_verilog -sv build.v" -p "synth_ice40 -relut -top ${SILICE_TOP} -json build.json"
 # nextpnr-ice40 --force --hx1k --json build.json --pcf $BOARD_DIR/icestick.pcf --asc build.asc --package tq144 --freq 12
 
 # icepack -s build.asc build.bin

frameworks/boards/tinytapeout/tinytapeout.v

@@ -12,7 +12,7 @@ $$ICE40=1
 `define SIM_SB_IO 1
 $$SIM_SB_IO=1
 
-module tt_um_silice (
+module %TOP_NAME% (
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path

frameworks/verilator/PWMAudio.cpp

@@ -31,7 +31,9 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include <iostream>
 #include <fstream>
 
-#define SAMPLE_FREQ 11025
+#define SAMPLE_FREQ (48828/4) // because its a nice multiple of 25MHz ...
+
+/// TODO: lots of assumptions here, generalize!
 
 // ----------------------------------------------------------------------------
 

src/SiliceCompiler.cpp

@@ -579,7 +579,7 @@ std::string SiliceCompiler::verilogTopModuleSignature(const std::map<std::string
 {
   std::string sig;
   for (const auto& P : used_pins) {
-    switch (P.second) 
+    switch (P.second)
     {
     case Input:  sig += "input  "; break;
     case Output: sig += "output "; break;
@@ -682,11 +682,12 @@ void SiliceCompiler::writeBody(const t_parsed_unit& parsed, std::ostream& _out,
     // update framework
     VerilogTemplate frmwrk;
     std::unordered_map<std::string, std::string> replacements;
+    replacements["TOP_NAME"]      = CONFIG.keyValues()["top_module_name"]; // top module name
     replacements["TOP_SIGNATURE"] = verilogTopModuleSignature(used_pins); // top module signature
     replacements["MAIN_GLUE"]     = verilogMainGlue(used_ports); // main module glue
     replacements["WIRE_DECL"]     = wire_decl; // main module wire declarations
     frmwrk.fromString(m_BodyContext->framework_verilog, replacements);
-    // write framework (top) module    
+    // write framework (top) module
     _out << frmwrk.code();
     // write includes
     for (auto fname : m_AppendsInDeclOrder) {
@@ -841,10 +842,10 @@ void SiliceCompiler::run(
   const std::vector<std::string>& defines,
   const std::vector<std::string>& configs,
   std::string to_export,
-  const std::vector<std::string>& export_params)
+  const std::vector<std::string>& export_params,
+  std::string top_module_name)
 {
   try {
-
     // create top instantiation context
     Blueprint::t_instantiation_context ictx;
     ictx.compiler = this;
@@ -862,6 +863,8 @@ void SiliceCompiler::run(
     }
     // begin parsing
     beginParsing(fsource, fresult, fframework, frameworks_dir, defines, ictx);
+    // configure top module name
+    CONFIG.keyValues()["top_module_name"] = top_module_name;
     // apply command line config options
     for (auto cfg : configs) {
       auto eq = cfg.find('=');

src/SiliceCompiler.h

@@ -110,7 +110,8 @@ namespace Silice {
       const std::vector<std::string>& defines,
       const std::vector<std::string>& configs,
       std::string to_export,
-      const std::vector<std::string>& export_params);
+      const std::vector<std::string>& export_params,
+      std::string top_module_name);
 
     /// \brief writes a unit in the output stream
     void writeUnit(

src/silice.cpp

@@ -86,10 +86,12 @@ int main(int argc, char **argv)
     cmd.add(exportParam);
     TCLAP::SwitchArg             forceResetInit("", "force-reset-init", "forces initialization at reset of initialized registers", false);
     cmd.add(forceResetInit);
-    TCLAP::SwitchArg             disableCL0006("", "no-pin-check", "disable check for pin declaration in frameworks (see CL0006)", true); /// ///////////////////////////////////////////// TODO set to false once no longer wip
+    TCLAP::SwitchArg             disableCL0006("", "no-pin-check", "disable check for pin declaration in frameworks (see CL0006)", true); /// ////////// TODO set to false once no longer wip
     cmd.add(disableCL0006);
     TCLAP::SwitchArg             splitInouts("", "split-inouts", "splits all inouts into enable, in, out pins", false);
     cmd.add(splitInouts);
+    TCLAP::ValueArg<std::string> top("", "top", "Name of the top module in generated Verilog", false, "top", "string");
+    cmd.add(top);
 
     cmd.parse(argc, argv);
 
@@ -106,7 +108,8 @@ int main(int argc, char **argv)
       defines.getValue(),
       configs.getValue(),
       toExport.getValue(),
-      exportParam.getValue());
+      exportParam.getValue(),
+      top.getValue());
 
   } catch (TCLAP::ArgException& err) {
     std::cerr << "command line error: " << err.what() << "\n";