Skip to content

Commit

Permalink
[test] Fix IRGen/yield_result.sil for 32-bit platforms
Browse files Browse the repository at this point in the history
Follow-up to 8b7a75c for 32-bit platforms.
  • Loading branch information
kateinoigakukun committed Aug 3, 2024
1 parent 650e90a commit dfad7b3
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions test/IRGen/yield_result.sil
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// RUN: %target-swift-frontend -emit-irgen %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize
// RUN: %target-swift-frontend -emit-irgen %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize -DINT=i%target-ptrsize

import Builtin

Expand Down Expand Up @@ -103,7 +103,7 @@ bb0(%outt : $*T, %t : $*T):
// CHECK: br i1 [[IS_UNWIND]], label %[[UNWIND_BB:.*]], label %[[RESUME_BB:.*]]

// CHECK:[[RESUME_BB]]:
// CHECK: [[VW_PTR:%.*]] = getelementptr inbounds ptr, ptr [[TYPE]], i64 -1
// CHECK: [[VW_PTR:%.*]] = getelementptr inbounds ptr, ptr [[TYPE]], [[INT]] -1
// CHECK: [[VW:%.*]] = load ptr, ptr [[VW_PTR]]
// CHECK: [[ASSIGN_PTR:%.*]] = getelementptr inbounds ptr, ptr [[VW]], i32 3
// CHECK: [[ASSIGN:%.*]] = load ptr, ptr [[ASSIGN_PTR]]
Expand All @@ -126,15 +126,15 @@ sil [ossa] @test_coro_ret_indirect : $(Builtin.Int64) -> () {
bb0(%0 : $Builtin.Int64):
// CHECK: [[ARG_COPY:%.*]] = alloca i64
// CHECK: [[INDIRECT_RET:%.*]] = alloca i64
// CHECK: [[FRAME:%.*]] = alloca [32 x i8]
// CHECK: [[FRAME:%.*]] = alloca [[[BUFFER_SIZE]] x i8]
%coro = function_ref @coro_ret_indirect : $@yield_once @convention(thin) <T> (@in T) -> (@yields @in T, @out T)
%temp = alloc_stack $Builtin.Int64
store %0 to [trivial] %temp : $*Builtin.Int64

%out = alloc_stack $Builtin.Int64

// CHECK: store i64 [[ARG]], ptr [[ARG_COPY]]
// CHECK: [[CTX:%.*]] = getelementptr inbounds [32 x i8], ptr [[FRAME]], i32 0, i32 0
// CHECK: [[CTX:%.*]] = getelementptr inbounds [[[BUFFER_SIZE]] x i8], ptr [[FRAME]], i32 0, i32 0
// CHECK: [[CORO:%.*]] = call ptr @llvm.coro.prepare.retcon(ptr @coro_ret_indirect)
// CHECK: [[FRAME:%.*]] = call swiftcc { ptr, ptr } [[CORO]](ptr{{.*}} [[CTX]], ptr [[INDIRECT_RET]], ptr noalias [[ARG_COPY]], ptr getelementptr inbounds (%swift.full_existential_type, ptr @{{.*}}

Expand Down

0 comments on commit dfad7b3

Please sign in to comment.