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Implement HPET driver #256
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Ready for reviews |
TODO: IOAPIC LOCAL APIC
TODO: enable main timer and wrap the wait event in some interface instead of using pit directly.
Also fake RTC irq as it's used by the hpet.
Also fix HPET frequency to 100ns
Also remove dead code
Somehow KVM doesn't use ACPI, fix issues on this.
Now ACPI is detected on KVM environments. Also updated multiboot2 crate to latest with our custom patches.
Test the hardware behaviour on partial write of the HPET accumulatorBecause we are running on i386, this cause issue on QEMU. In fact, QEMU clear the accumulator flag on every partial write. The question here is: Is that normal or a bug in QEMU? SunriseOS/kernel/src/devices/hpet.rs Lines 232 to 242 in 8e5ee83
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enable main timerSunriseOS/kernel/src/devices/hpet.rs Lines 431 to 441 in 8e5ee83
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remove this when IO-APIC will be implementedSunriseOS/kernel/src/devices/hpet.rs Lines 464 to 474 in 8e5ee83
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switch HPET to normal mode when IO-APIC will be implemented.SunriseOS/kernel/src/devices/hpet.rs Lines 478 to 488 in 8e5ee83
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Rebased |
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Math is hard
I don't recall what was the precise reason of this PR ? Did we need a higher precision timer somewhere ? Is this a necessary step to some goal ? |
@Orycterope This is a preparation to get the LAPIC and IO-APIC implemented (and then multicore). The final goal of this is to have multiple timer on multiple core. |
Switch to a lower update frequency in HPETWe will maybe prefer to have a better resolution for kernel time. For that to be possible, we need to take care of the sleep_thread logic in userland first (sleep_thread(0) shouldn't be used). SunriseOS/kernel/src/devices/hpet.rs Lines 449 to 459 in dce8599
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Also update documentation
This PR adds support for the "High Precision Event Timer" device.
This permits us to get better timing resolution (PIC resolution was 10ms, we now have a resolution of 100ns)
As we currently don't have IO-APIC support, the HPET is setup in "legacy mapping" and use the IRQ0 and IRQ8 for timer 0 and timer 1.
This result in the RTC device not being able to send interrupt.
For this matter, the timer 1 is setup to send an interrupt every seconds to fake this until we get IO-APIC support.