[rtl] remove redundant code

rtl/core/neorv32_cpu_cp_muldiv.vhd

@@ -191,7 +191,7 @@ begin
   -- Multiplier Core (signed/unsigned) - Full Parallel --------------------------------------
   -- -------------------------------------------------------------------------------------------
   multiplier_core_parallel:
-  if (FAST_MUL_EN = true) generate
+  if FAST_MUL_EN generate
 
     -- direct approach --
     multiplier_core: process(rstn_i, clk_i)
@@ -216,7 +216,7 @@ begin
 
   -- no parallel multiplier --
   multiplier_core_parallel_none:
-  if (FAST_MUL_EN = false) generate
+  if not FAST_MUL_EN generate
     mul.dsp_x <= (others => '0');
     mul.dsp_y <= (others => '0');
     mul.dsp_z <= (others => '0');
@@ -226,7 +226,7 @@ begin
   -- Multiplier Core (signed/unsigned) - Iterative ------------------------------------------
   -- -------------------------------------------------------------------------------------------
   multiplier_core_serial:
-  if (FAST_MUL_EN = false) generate
+  if not FAST_MUL_EN generate
 
     -- shift-and-add algorithm --
     multiplier_core: process(rstn_i, clk_i)
@@ -265,7 +265,7 @@ begin
 
   -- no serial multiplier --
   multiplier_core_serial_none:
-  if (FAST_MUL_EN = true) generate
+  if FAST_MUL_EN generate
     mul.add    <= (others => '0');
     mul.p_sext <= '0';
   end generate;
@@ -274,7 +274,7 @@ begin
   -- Divider Core (unsigned) - Iterative ----------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   divider_core_serial:
-  if (DIVISION_EN = true) generate
+  if DIVISION_EN generate
 
     -- restoring division algorithm --
     divider_core: process(rstn_i, clk_i)
@@ -312,7 +312,7 @@ begin
 
   -- no divider --
   divider_core_serial_none:
-  if (DIVISION_EN = false) generate
+  if not DIVISION_EN generate
     div.remainder <= (others => '0');
     div.quotient  <= (others => '0');
     div.sub       <= (others => '0');

rtl/core/neorv32_cpu_cp_shifter.vhd

@@ -84,7 +84,7 @@ begin
   -- Serial Shifter (small but slow) --------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   serial_shifter:
-  if (FAST_SHIFT_EN = false) generate
+  if not FAST_SHIFT_EN generate
 
     serial_shifter_core: process(rstn_i, clk_i)
     begin
@@ -127,7 +127,7 @@ begin
   -- Barrel Shifter (fast but large) --------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   barrel_shifter:
-  if (FAST_SHIFT_EN = true) generate
+  if FAST_SHIFT_EN generate
 
     -- shifter core --
     barrel_shifter_core: process(rs1_i, shamt_i, ctrl_i, bs_level)

rtl/core/neorv32_package.vhd

@@ -56,7 +56,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090203"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090204"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width, do not change!
 
@@ -922,7 +922,7 @@ end neorv32_package;
 package body neorv32_package is
 
 -- ****************************************************************************************************************************
--- Functions
+-- Helper Functions
 -- ****************************************************************************************************************************
 
   -- Minimal required number of bits to represent <input> numbers ---------------------------
@@ -941,7 +941,7 @@ package body neorv32_package is
   -- -------------------------------------------------------------------------------------------
   function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer is
   begin
-    if (cond = true) then
+    if cond then
       return val_t;
     else
       return val_f;
@@ -952,7 +952,7 @@ package body neorv32_package is
   -- -------------------------------------------------------------------------------------------
   function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
   begin
-    if (cond = true) then
+    if cond then
       return val_t;
     else
       return val_f;
@@ -963,7 +963,7 @@ package body neorv32_package is
   -- -------------------------------------------------------------------------------------------
   function cond_sel_suv_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
   begin
-    if (cond = true) then
+    if cond then
       return val_t;
     else
       return val_f;
@@ -974,7 +974,7 @@ package body neorv32_package is
   -- -------------------------------------------------------------------------------------------
   function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string is
   begin
-    if (cond = true) then
+    if cond then
       return val_t;
     else
       return val_f;
@@ -985,7 +985,7 @@ package body neorv32_package is
   -- -------------------------------------------------------------------------------------------
   function bool_to_ulogic_f(cond : boolean) return std_ulogic is
   begin
-    if (cond = true) then
+    if cond then
       return '1';
     else
       return '0';
@@ -1068,8 +1068,8 @@ package body neorv32_package is
     variable hex_v : string(1 to 16);
   begin
     hex_v := "0123456789abcdef";
-    if (su_undefined_f(input(3)) = true) or (su_undefined_f(input(2)) = true) or
-       (su_undefined_f(input(1)) = true) or (su_undefined_f(input(0)) = true) then
+    if su_undefined_f(input(3)) or su_undefined_f(input(2)) or
+       su_undefined_f(input(1)) or su_undefined_f(input(0)) then
       return '?';
     else
       return hex_v(to_integer(unsigned(input)) + 1);