Merge pull request #69 from stnolting/dependabot/submodules/neorv32-c… · stnolting/neorv32-verilog@3a79ead

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Merge pull request #69 from stnolting/dependabot/submodules/neorv32-c…

…303756

[Dependabot]: Bump neorv32 from `21fea6d` to `c303756`

stnolting authored Dec 4, 2023

2 parents b9de186 + ce57133 commit 3a79ead

neorv32

Submodule neorv32 updated 30 files

+151 −147		CHANGELOG.md
+2 −1		README.md
+1 −1		docs/attrs.adoc
+46 −26		docs/datasheet/cpu.adoc
+40 −5		docs/datasheet/cpu_csr.adoc
+57 −59		docs/datasheet/on_chip_debugger.adoc
+36 −34		docs/datasheet/overview.adoc
+1 −0		docs/datasheet/soc.adoc
+1 −1		docs/datasheet/soc_cfs.adoc
+5 −0		docs/datasheet/software_bootloader.adoc
+10 −0		docs/datasheet/software_rte.adoc
+ −		docs/figures/neorv32_processor.png
+ −		docs/references/riscv-debug-stable.pdf
+ −		docs/references/riscv-zicond_1.0.1.pdf
+4 −0		docs/userguide/executable_upload.adoc
+12 −9		rtl/core/neorv32_cpu.vhd
+54 −22		rtl/core/neorv32_cpu_alu.vhd
+175 −94		rtl/core/neorv32_cpu_control.vhd
+86 −0		rtl/core/neorv32_cpu_cp_cond.vhd
+7 −4		rtl/core/neorv32_package.vhd
+2 −0		rtl/core/neorv32_top.vhd
+2 −1		sim/neorv32_tb.vhd
+1 −0		sim/simple/neorv32_tb.simple.vhd
+0 −110		sw/example/demo_trigger_module/main.c
+0 −4		sw/example/demo_trigger_module/makefile
+92 −26		sw/example/processor_check/main.c
+8 −6		sw/lib/include/neorv32_cpu_csr.h
+1 −0		sw/lib/include/neorv32_rte.h
+119 −19		sw/lib/source/neorv32_rte.c
+1 −1		sw/svd/neorv32.svd

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