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BLE on the stm32wb55 #17

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Merged
merged 7 commits into from
Dec 1, 2020
Merged

BLE on the stm32wb55 #17

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f7dbf18
Support of the shared memory transport layer for the stm32wb55
FRASTM Nov 4, 2020
3019930
Include the STM32Cube_FW to support the BLE of the stm32wb55
FRASTM Oct 13, 2020
732ffed
This BLE RF configuration has many unused define values
FRASTM Nov 12, 2020
163bd85
Missing IPCC enable for C2 in several examples from stm32CubeWB
FRASTM Nov 12, 2020
19df1cb
Add shared memory transport layer for the stm32wb55
FRASTM Nov 5, 2020
0660a94
Fix [-Waddress-of-packed-member] warning
FRASTM Nov 19, 2020
8f0e116
Modify the examples to run on the nucleo_wb55rg board
FRASTM Sep 25, 2020
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Missing IPCC enable for C2 in several examples from stm32CubeWB 
This fix is coming from
STMicroelectronics/STM32CubeWB#19

Signed-off-by: Francois Ramu <francois.ramu@st.com>
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@FRASTM
FRASTM committed Dec 1, 2020
commit 163bd85bf724a6d4f17c48ae051bd6ca1a108c3d
6 changes: 6 additions & 0 deletions src/utility/STM32Cube_FW/hw_ipcc.c
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Expand Up @@ -94,6 +94,12 @@ void IPCC_C1_TX_IRQHandler(void)
******************************************************************************/
void HW_IPCC_Enable(void)
{
/**
* Such as IPCC IP available to the CPU2, it is required to keep the IPCC clock running
when FUS is running on CPU2 and CPU1 enters deep sleep mode
*/
LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC);

/**
* When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
*/
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