MemHierarchy TLB in interface

src/sst/elements/balar/balarMMIO.cc

@@ -164,7 +164,7 @@ void BalarMMIO::send_read_request_SST(unsigned core_id, uint64_t address, uint64
     numPendingCacheTransPerCore[core_id]++;
     gpu_to_cache_links[core_id]->send(req);
 
-    out.verbose(CALL_INFO, 1, 0, "Sent a read request with id (%ld) to addr %lx\n", req->getID(), req->pAddr);
+    out.verbose(CALL_INFO, 1, 0, "Sent a read request with id (%ld) to addr %lx\n", req->getID(), req->vAddr);
 }
 
 /**
@@ -185,7 +185,7 @@ void BalarMMIO::send_write_request_SST(unsigned core_id, uint64_t address, uint6
     gpuCachePendingTransactions->insert(std::pair<StandardMem::Request::id_t, cache_req_params>(req->getID(), cache_req_params(core_id, mem_req, req)));
     numPendingCacheTransPerCore[core_id]++;
     gpu_to_cache_links[core_id]->send(req);
-    out.verbose(CALL_INFO, 1, 0, "Sent a write request with id (%ld) to addr: %lx\n", req->getID(), req->pAddr);
+    out.verbose(CALL_INFO, 1, 0, "Sent a write request with id (%ld) to addr: %lx\n", req->getID(), req->vAddr);
 }
 
 /**

src/sst/elements/balar/dmaEngine.cc

@@ -250,7 +250,7 @@ void DMAEngine::DMAHandlers::handle(StandardMem::ReadResp* resp) {
 
     // Find the simulator buffer pointer value by offset
     // of the sst mem space addr
-    size_t offset = resp->pAddr - dma_req->sst_mem_addr;
+    size_t offset = resp->vAddr - dma_req->sst_mem_addr;
     uint8_t * offseted_ptr = dma_req->simulator_mem_addr + offset;
 
     // Perform copy from response

src/sst/elements/balar/tests/balarBlock.py

@@ -308,19 +308,10 @@ def buildVanadisIntegration(self, cfgFile, balar_verbosity=0, dma_verbosity=0):
             "tlb_set_size": 4,
         }
 
-        balarTlbWrapperParams = {
-            "debug_level": 0,
-        }
-        balarTlbWrapper = sst.Component("balarTlb", "mmu.tlb_wrapper")
-        balarTlbWrapper.addParams(balarTlbWrapperParams)
-        balarTlb = balarTlbWrapper.setSubComponent("tlb", "mmu.simpleTLB")
+        balarTlb = dma_mem_if.setSubComponent("tlb", "mmu.simpleTLB")
         balarTlb.addParams(balarTlbParams)
 
-        # Connect the data link for dmaEngine to TLB
-        connect("balar_balarBus_link", dma_mem_if, "lowlink",
-                balarTlbWrapper, "cpu_if", "1ns")
-
         # mem_iface replaced by TLB, keep mmio_iface
-        return balarTlbWrapper, balarTlb, balar_mmio_iface, dma_mmio_if
+        return dma_mem_if, balarTlb, balar_mmio_iface, dma_mmio_if
 
 

src/sst/elements/balar/tests/memory.py

@@ -4,8 +4,8 @@
 
 coherence_protocol="MESI"
 
-dc_debug = 1
-mc_debug = 1
+dc_debug = 0
+mc_debug = 0
 stdMem_debug = 0
 
 debug_addr = 0x6280

src/sst/elements/balar/tests/testBalar-testcpu.py

@@ -40,7 +40,7 @@
 DEBUG_NIC = 0
 DEBUG_LEVEL = 10
 
-debug_params = {"debug": 1, "debug_level": 10}
+debug_params = {"debug": 0, "debug_level": 10}
 
 # On network: Core, L1, MMIO device, memory
 # Logical communication: Core->L1->memory

src/sst/elements/balar/tests/testBalar-vanadis.py

@@ -67,14 +67,14 @@
 # ===========================================================
 # build the Vanadis CPU block, this returns
 # cpu, L2 cache, DTLB ITLB
-cpu, L1, l1dcache_2_cpu, L2, dtlb, coredtlbWrapper, itlb = cpuBuilder.build(nodeId,0)
+cpu, L1, l1dcache_2_cpu, L2, dtlb, coredcache_iface, itlb = cpuBuilder.build(nodeId,0)
 
 # build the Vanadis OS, it returns
 # OS cache
 osCache = osBuilder.build(numNodes, nodeId, 0)
 
 # Build balar
-balarTlbWrapper, balarTlb, balar_mmio_iface, dma_mmio_if = balarBuilder.buildVanadisIntegration(cfgFile, verbosity, dma_verbosity)
+balar_dma_iface, balarTlb, balar_mmio_iface, dma_mmio_if = balarBuilder.buildVanadisIntegration(cfgFile, verbosity, dma_verbosity)
 
 # Build CPU memory
 numPorts = 4
@@ -94,9 +94,9 @@
 })
 
 # Connect the mem links for coreTLB and balarTLB
-connect("coreTLB_coreCacheBus_link", balarTlbWrapper, "cache_if",
+connect("coreTLB_coreCacheBus_link", balar_dma_iface, "lowlink",
         coreCacheBus, "highlink0", "1ns")
-connect("balarTLB_coreCacheBus_link", coredtlbWrapper, "cache_if",
+connect("balarTLB_coreCacheBus_link", coredcache_iface, "lowlink",
         coreCacheBus, "highlink1", "1ns")
 connect("coreCacheBus_l1cache_link", coreCacheBus, "lowlink0",
         l1dcache_2_cpu, "port", "1ns")

src/sst/elements/balar/tests/vanadisBlock.py

@@ -50,17 +50,13 @@
     print( "Verbosity: " + str(verbosity) + " -> loading Vanadis CPU type: " + vanadis_cpu_type )
 
 tlbParams = {
-    "debug_level": 10,
+    "debug_level": 0,
     "hit_latency": 10,
     "num_hardware_threads": 1,
     "num_tlb_entries_per_thread": 64,
     "tlb_set_size": 4,
 }
 
-tlbWrapperParams = {
-    "debug_level": 10,
-}
-
 class Vanadis_Builder:
     def __init__(self, args={}):
         self.args = args
@@ -132,7 +128,6 @@ def build( self, nodeId, cpuId ):
         cpu_lsq.enableAllStatistics()
 
         dcache_if = cpu_lsq.setSubComponent( "memory_interface", "memHierarchy.standardInterface" )
-        dcache_if.addParam("coreId",cpuId)
         dcache_if.addParams( {
             "debug" : stdMem_debug,
             "debug_level" : 11,
@@ -200,25 +195,13 @@ def build( self, nodeId, cpuId ):
         l2cache_2_cpu = l2cache.setSubComponent("highlink", "memHierarchy.MemLink")
 
         # CPU D-TLB
-        dtlbWrapper = sst.Component(prefix+".dtlb", "mmu.tlb_wrapper")
-        dtlbWrapper.addParams(tlbWrapperParams)
-        dtlb = dtlbWrapper.setSubComponent("tlb", "mmu.simpleTLB" )
+        dtlb = dcache_if.setSubComponent("tlb", "mmu.simpleTLB")
         dtlb.addParams(tlbParams)
 
         # CPU I-TLB
-        itlbWrapper = sst.Component(prefix+".itlb", "mmu.tlb_wrapper")
-        itlbWrapper.addParams(tlbWrapperParams)
-        itlbWrapper.addParam("exe",True)
-        itlb = itlbWrapper.setSubComponent("tlb", "mmu.simpleTLB" );
+        itlb = icache_if.setSubComponent("tlb", "mmu.simpleTLB")
         itlb.addParams(tlbParams)
-
-        # CPU (data) -> D-TLB
-        link = sst.Link(prefix+".link_cpu_dtlb")
-        link.connect( (dcache_if, "lowlink", "1ns"), (dtlbWrapper, "cpu_if", "1ns") )
-
-        # CPU (instruction) -> I-TLB
-        link = sst.Link(prefix+".link_cpu_itlb")
-        link.connect( (icache_if, "lowlink", "1ns"), (itlbWrapper, "cpu_if", "1ns") )
+        itlb.addParam("tlb_exe_permission",True)
 
         l1icache_2_cpu     = l1icache.setSubComponent("highlink", "memHierarchy.MemLink")
         l1icache_2_l2cache = l1icache.setSubComponent("lowlink", "memHierarchy.MemLink")
@@ -230,7 +213,7 @@ def build( self, nodeId, cpuId ):
 
         # I-TLB -> I-L1
         link = sst.Link(prefix+".link_l1icache")
-        link.connect( (itlbWrapper, "cache_if", "1ns"), (l1icache_2_cpu, "port", "1ns") )
+        link.connect( (icache_if, "lowlink", "1ns"), (l1icache_2_cpu, "port", "1ns") )
 
         # L1 I-Cache to bus
         link = sst.Link(prefix + ".link_l1dcache_l2cache")
@@ -244,4 +227,4 @@ def build( self, nodeId, cpuId ):
         link = sst.Link(prefix+".link_bus_l2cache")
         link.connect( (cache_bus, "lowlink0", "1ns"), (l2cache_2_cpu, "port", "1ns") )
 
-        return cpu, l1cache, l1dcache_2_cpu, l2cache, dtlb, dtlbWrapper, itlb
+        return cpu, l1cache, l1dcache_2_cpu, l2cache, dtlb, dcache_if, itlb

src/sst/elements/balar/tests/vanadisOS.py

@@ -101,11 +101,10 @@ def build( self, numNodes, nodeId, cpuId ):
             "num_cores": 1,
             "num_threads": 1,
             "page_size": 4096,
-            "useNicTlb": True,
+            "use_nic_tlb": True,
         })
 
         mem_if = self.nodeOS.setSubComponent( "mem_interface", "memHierarchy.standardInterface" )
-        mem_if.addParam("coreId",cpuId)
         mem_if.addParams({
             "debug" : stdMem_debug,
             "debug_level" : 11,

src/sst/elements/golem/tests/basic_golem.py

@@ -457,22 +457,22 @@ def build( self, prefix, nodeId, cpuId ):
 
         # processor_bus -> L1 cache
         link_bus_l1cache_link = sst.Link(prefix+".link_bus_l1cache_link")
-        link_bus_l1cache_link.connect( (processor_bus, "lowlink0", "1ns"), (dtlbWrapper, "cpu_if", "1ns") )
+        link_bus_l1cache_link.connect( (processor_bus, "lowlink0", "1ns"), (dtlbWrapper, "highlink", "1ns") )
         link_bus_l1cache_link.setNoCut()
 
         # data TLB -> data L1
         link_cpu_l1dcache_link = sst.Link(prefix+".link_cpu_l1dcache_link")
-        link_cpu_l1dcache_link.connect( (dtlbWrapper, "cache_if", "1ns"), (l1dcache_2_cpu, "port", "1ns") )
+        link_cpu_l1dcache_link.connect( (dtlbWrapper, "lowlink", "1ns"), (l1dcache_2_cpu, "port", "1ns") )
         link_cpu_l1dcache_link.setNoCut()
 
         # CPU (instruction) -> TLB -> Cache
         link_cpu_itlb_link = sst.Link(prefix+".link_cpu_itlb_link")
-        link_cpu_itlb_link.connect( (cpuIcacheIf, "lowlink", "1ns"), (itlbWrapper, "cpu_if", "1ns") )
+        link_cpu_itlb_link.connect( (cpuIcacheIf, "lowlink", "1ns"), (itlbWrapper, "highlink", "1ns") )
         link_cpu_itlb_link.setNoCut()
 
         # instruction TLB -> instruction L1
         link_cpu_l1icache_link = sst.Link(prefix+".link_cpu_l1icache_link")
-        link_cpu_l1icache_link.connect( (itlbWrapper, "cache_if", "1ns"), (l1icache_2_cpu, "port", "1ns") )
+        link_cpu_l1icache_link.connect( (itlbWrapper, "lowlink", "1ns"), (l1icache_2_cpu, "port", "1ns") )
         link_cpu_l1icache_link.setNoCut()
 
         # data L1 -> bus