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Merged
sst-autotester merged 4 commits into from
Jan 30, 2026
+12,596 −12,546
Merged

SST Master Branch Merger: Auto Create Pull Request to Promote from devel to master - All Tests Ran Clean #2630

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a0733f7
Event order update (#2627)
feldergast Jan 26, 2026
a75ec03
Update reference files found by nightlies for event order update. (#2…
feldergast Jan 27, 2026
3ba8394
MMU error checking and clean up (#2621)
gvoskuilen Jan 28, 2026
955cf53
rdmaNic: Fix ref for sst-core ordering change (#2629)
gvoskuilen Jan 28, 2026
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2 changes: 1 addition & 1 deletion src/sst/elements/balar/tests/balarBlock.py
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Expand Up @@ -302,7 +302,7 @@ def buildVanadisIntegration(self, cfgFile, balar_verbosity=0, dma_verbosity=0):
# Balar TLB
balarTlbParams = {
"debug_level": 0,
"hitLatency": 10,
"hit_latency": 10,
"num_hardware_threads": 1,
"num_tlb_entries_per_thread": 64,
"tlb_set_size": 4,
Expand Down
2 changes: 1 addition & 1 deletion src/sst/elements/balar/tests/vanadisBlock.py
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Expand Up @@ -51,7 +51,7 @@

tlbParams = {
"debug_level": 10,
"hitLatency": 10,
"hit_latency": 10,
"num_hardware_threads": 1,
"num_tlb_entries_per_thread": 64,
"tlb_set_size": 4,
Expand Down
6 changes: 3 additions & 3 deletions src/sst/elements/cacheTracer/tests/refFiles/test_cacheTracer_1.out
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Expand Up @@ -43,8 +43,8 @@ Access Latency Distribution (ns):
Min-Latency(ns): 3 Max-Latency(ns): 175 #Bins: 10
-----------------------------------------------------------------
Latency Range(ns): Count
- [0-17]: 259
- [18-35]: 2
- [0-17]: 258
- [18-35]: 3
- [36-53]: 1
- [54-71]: 0
- [72-89]: 1
Expand All @@ -57,4 +57,4 @@ Latency Range(ns): Count
- Total_Events_Latency: 1000
-----------------------------------------------------------------

Simulation is complete, simulated time: 6.17 us
Simulation is complete, simulated time: 6.173 us
2 changes: 1 addition & 1 deletion src/sst/elements/golem/tests/basic_golem.py
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Expand Up @@ -205,7 +205,7 @@
# CPU related params
tlbParams = {
"debug_level": 0,
"hitLatency": 1,
"hit_latency": 1,
"num_hardware_threads": numThreads,
"num_tlb_entries_per_thread": 64,
"tlb_set_size": 4,
Expand Down
948 changes: 474 additions & 474 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining.out
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946 changes: 473 additions & 473 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer.out
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40 changes: 20 additions & 20 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDramsim3.out
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86 changes: 43 additions & 43 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC.out
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302 changes: 151 additions & 151 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendRamulator_1.out
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602 changes: 301 additions & 301 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendRamulator_2.out
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894 changes: 447 additions & 447 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow.out
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834 changes: 417 additions & 417 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple.out
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42 changes: 21 additions & 21 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1.out
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38 changes: 19 additions & 19 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2.out
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46 changes: 23 additions & 23 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1.out
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46 changes: 23 additions & 23 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2.out
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46 changes: 23 additions & 23 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3.out
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46 changes: 23 additions & 23 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4.out
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30 changes: 15 additions & 15 deletions src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim.out
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Expand Up @@ -97,7 +97,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr
l1cache0.msi.evict_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1;
l1cache0.msi.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l1cache0.msi.latency_GetS_hit : Accumulator : Sum.u64 = 68707; SumSQ.u64 = 1194691829; Count.u64 = 9; Min.u64 = 6; Max.u64 = 26351;
l1cache0.msi.latency_GetS_miss : Accumulator : Sum.u64 = 75227902; SumSQ.u64 = 2047175032768; Count.u64 = 3014; Min.u64 = 114; Max.u64 = 57739;
l1cache0.msi.latency_GetS_miss : Accumulator : Sum.u64 = 75227902; SumSQ.u64 = 2047175031042; Count.u64 = 3014; Min.u64 = 114; Max.u64 = 57739;
l1cache0.msi.latency_GetX_hit : Accumulator : Sum.u64 = 1729; SumSQ.u64 = 2968765; Count.u64 = 2; Min.u64 = 6; Max.u64 = 1723;
l1cache0.msi.latency_GetX_miss : Accumulator : Sum.u64 = 50449872; SumSQ.u64 = 1372092705190; Count.u64 = 1966; Min.u64 = 113; Max.u64 = 53419;
l1cache0.msi.latency_GetX_upgrade : Accumulator : Sum.u64 = 229177; SumSQ.u64 = 6865837641; Count.u64 = 9; Min.u64 = 113; Max.u64 = 39595;
Expand Down Expand Up @@ -257,9 +257,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr
l1cache1.msi.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l1cache1.msi.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l1cache1.msi.latency_GetS_hit : Accumulator : Sum.u64 = 90959; SumSQ.u64 = 1850541141; Count.u64 = 14; Min.u64 = 6; Max.u64 = 26639;
l1cache1.msi.latency_GetS_miss : Accumulator : Sum.u64 = 73656494; SumSQ.u64 = 1997491916740; Count.u64 = 2962; Min.u64 = 113; Max.u64 = 59755;
l1cache1.msi.latency_GetS_miss : Accumulator : Sum.u64 = 73656493; SumSQ.u64 = 1997491958817; Count.u64 = 2962; Min.u64 = 113; Max.u64 = 59755;
l1cache1.msi.latency_GetX_hit : Accumulator : Sum.u64 = 26189; SumSQ.u64 = 685863721; Count.u64 = 1; Min.u64 = 26189; Max.u64 = 26189;
l1cache1.msi.latency_GetX_miss : Accumulator : Sum.u64 = 51403815; SumSQ.u64 = 1390789448697; Count.u64 = 2012; Min.u64 = 113; Max.u64 = 51948;
l1cache1.msi.latency_GetX_miss : Accumulator : Sum.u64 = 51403816; SumSQ.u64 = 1390789494632; Count.u64 = 2012; Min.u64 = 113; Max.u64 = 51948;
l1cache1.msi.latency_GetX_upgrade : Accumulator : Sum.u64 = 348967; SumSQ.u64 = 11843616965; Count.u64 = 11; Min.u64 = 24644; Max.u64 = 51646;
l1cache1.msi.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l1cache1.msi.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
Expand Down Expand Up @@ -459,10 +459,10 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr
l2cache0.msi.inclus.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l2cache0.msi.inclus.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l2cache0.msi.inclus.latency_GetS_hit : Accumulator : Sum.u64 = 57808; SumSQ.u64 = 1059861372; Count.u64 = 138; Min.u64 = 21; Max.u64 = 21619;
l2cache0.msi.inclus.latency_GetS_miss : Accumulator : Sum.u64 = 142058108; SumSQ.u64 = 3639573877922; Count.u64 = 5831; Min.u64 = 208; Max.u64 = 50859;
l2cache0.msi.inclus.latency_GetS_miss : Accumulator : Sum.u64 = 142058106; SumSQ.u64 = 3639573863876; Count.u64 = 5831; Min.u64 = 208; Max.u64 = 50859;
l2cache0.msi.inclus.latency_GetS_inv : Accumulator : Sum.u64 = 84112; SumSQ.u64 = 1469430128; Count.u64 = 7; Min.u64 = 114; Max.u64 = 25888;
l2cache0.msi.inclus.latency_GetX_hit : Accumulator : Sum.u64 = 588; SumSQ.u64 = 12348; Count.u64 = 28; Min.u64 = 21; Max.u64 = 21;
l2cache0.msi.inclus.latency_GetX_miss : Accumulator : Sum.u64 = 96293207; SumSQ.u64 = 2482285350303; Count.u64 = 3881; Min.u64 = 208; Max.u64 = 51166;
l2cache0.msi.inclus.latency_GetX_miss : Accumulator : Sum.u64 = 96293204; SumSQ.u64 = 2482285287434; Count.u64 = 3881; Min.u64 = 208; Max.u64 = 51166;
l2cache0.msi.inclus.latency_GetX_inv : Accumulator : Sum.u64 = 57183; SumSQ.u64 = 769553225; Count.u64 = 8; Min.u64 = 114; Max.u64 = 16415;
l2cache0.msi.inclus.latency_GetX_upgrade : Accumulator : Sum.u64 = 2008085; SumSQ.u64 = 52313733353; Count.u64 = 81; Min.u64 = 208; Max.u64 = 39790;
l2cache0.msi.inclus.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
Expand Down Expand Up @@ -530,7 +530,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr
l2cache0.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l2cache0.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1;
l2cache0.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l2cache0.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 240606932; SumSQ.u64 = 14720663450; Count.u64 = 3955236; Min.u64 = 0; Max.u64 = 65;
l2cache0.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 240606926; SumSQ.u64 = 14720662722; Count.u64 = 3955236; Min.u64 = 0; Max.u64 = 65;
l2cache0.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
core2.pendCycle : Accumulator : Sum.u64 = 125544070; SumSQ.u64 = 4012469060; Count.u64 = 3935220; Min.u64 = 0; Max.u64 = 32;
core2.reads : Accumulator : Sum.u64 = 2976; SumSQ.u64 = 2976; Count.u64 = 2976; Min.u64 = 1; Max.u64 = 1;
Expand Down Expand Up @@ -627,9 +627,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr
l1cache2.msi.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l1cache2.msi.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l1cache2.msi.latency_GetS_hit : Accumulator : Sum.u64 = 90623; SumSQ.u64 = 1833928065; Count.u64 = 14; Min.u64 = 6; Max.u64 = 26639;
l1cache2.msi.latency_GetS_miss : Accumulator : Sum.u64 = 73656538; SumSQ.u64 = 1997423487338; Count.u64 = 2962; Min.u64 = 113; Max.u64 = 59755;
l1cache2.msi.latency_GetS_miss : Accumulator : Sum.u64 = 73656533; SumSQ.u64 = 1997423222207; Count.u64 = 2962; Min.u64 = 113; Max.u64 = 59755;
l1cache2.msi.latency_GetX_hit : Accumulator : Sum.u64 = 25647; SumSQ.u64 = 657460917; Count.u64 = 2; Min.u64 = 6; Max.u64 = 25641;
l1cache2.msi.latency_GetX_miss : Accumulator : Sum.u64 = 51429734; SumSQ.u64 = 1392150198390; Count.u64 = 2012; Min.u64 = 113; Max.u64 = 52211;
l1cache2.msi.latency_GetX_miss : Accumulator : Sum.u64 = 51429739; SumSQ.u64 = 1392150431323; Count.u64 = 2012; Min.u64 = 113; Max.u64 = 52211;
l1cache2.msi.latency_GetX_upgrade : Accumulator : Sum.u64 = 321528; SumSQ.u64 = 11066310384; Count.u64 = 10; Min.u64 = 24718; Max.u64 = 51403;
l1cache2.msi.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l1cache2.msi.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
Expand Down Expand Up @@ -989,10 +989,10 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr
l2cache1.msi.inclus.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l2cache1.msi.inclus.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l2cache1.msi.inclus.latency_GetS_hit : Accumulator : Sum.u64 = 85260; SumSQ.u64 = 1234808418; Count.u64 = 130; Min.u64 = 21; Max.u64 = 24561;
l2cache1.msi.inclus.latency_GetS_miss : Accumulator : Sum.u64 = 141622008; SumSQ.u64 = 3625153344034; Count.u64 = 5801; Min.u64 = 208; Max.u64 = 51022;
l2cache1.msi.inclus.latency_GetS_miss : Accumulator : Sum.u64 = 141622002; SumSQ.u64 = 3625153028746; Count.u64 = 5801; Min.u64 = 208; Max.u64 = 51022;
l2cache1.msi.inclus.latency_GetS_inv : Accumulator : Sum.u64 = 112976; SumSQ.u64 = 1916720918; Count.u64 = 14; Min.u64 = 114; Max.u64 = 23485;
l2cache1.msi.inclus.latency_GetX_hit : Accumulator : Sum.u64 = 483; SumSQ.u64 = 10143; Count.u64 = 23; Min.u64 = 21; Max.u64 = 21;
l2cache1.msi.inclus.latency_GetX_miss : Accumulator : Sum.u64 = 97577941; SumSQ.u64 = 2504048783233; Count.u64 = 3937; Min.u64 = 208; Max.u64 = 42248;
l2cache1.msi.inclus.latency_GetX_miss : Accumulator : Sum.u64 = 97577947; SumSQ.u64 = 2504049000857; Count.u64 = 3937; Min.u64 = 208; Max.u64 = 42248;
l2cache1.msi.inclus.latency_GetX_inv : Accumulator : Sum.u64 = 51003; SumSQ.u64 = 1071713655; Count.u64 = 4; Min.u64 = 114; Max.u64 = 25617;
l2cache1.msi.inclus.latency_GetX_upgrade : Accumulator : Sum.u64 = 1634817; SumSQ.u64 = 45734722693; Count.u64 = 63; Min.u64 = 451; Max.u64 = 52030;
l2cache1.msi.inclus.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
Expand Down Expand Up @@ -1060,7 +1060,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr
l2cache1.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l2cache1.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1;
l2cache1.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l2cache1.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 241126308; SumSQ.u64 = 14756307826; Count.u64 = 3955236; Min.u64 = 0; Max.u64 = 65;
l2cache1.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 241126306; SumSQ.u64 = 14756307596; Count.u64 = 3955236; Min.u64 = 0; Max.u64 = 65;
l2cache1.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l3cache.msi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 3981555; SumSQ.u64 = 577325475; Count.u64 = 27459; Min.u64 = 145; Max.u64 = 145;
l3cache.msi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 8473792; SumSQ.u64 = 4410978304; Count.u64 = 27459; Min.u64 = 64; Max.u64 = 576;
Expand Down Expand Up @@ -1202,12 +1202,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr
l3cache.msi.inclus.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l3cache.msi.inclus.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l3cache.msi.inclus.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l3cache.msi.inclus.latency_GetS_hit : Accumulator : Sum.u64 = 69846523; SumSQ.u64 = 1773222838951; Count.u64 = 3024; Min.u64 = 101; Max.u64 = 50050;
l3cache.msi.inclus.latency_GetS_hit : Accumulator : Sum.u64 = 69846505; SumSQ.u64 = 1773222020581; Count.u64 = 3024; Min.u64 = 101; Max.u64 = 50050;
l3cache.msi.inclus.latency_GetS_miss : Accumulator : Sum.u64 = 212345129; SumSQ.u64 = 5426782802229; Count.u64 = 8488; Min.u64 = 1366; Max.u64 = 50914;
l3cache.msi.inclus.latency_GetS_inv : Accumulator : Sum.u64 = 232831; SumSQ.u64 = 3634887403; Count.u64 = 120; Min.u64 = 236; Max.u64 = 25947;
l3cache.msi.inclus.latency_GetX_hit : Accumulator : Sum.u64 = 2626; SumSQ.u64 = 265226; Count.u64 = 26; Min.u64 = 101; Max.u64 = 101;
l3cache.msi.inclus.latency_GetX_miss : Accumulator : Sum.u64 = 141689091; SumSQ.u64 = 3623104263341; Count.u64 = 5654; Min.u64 = 1079; Max.u64 = 51058;
l3cache.msi.inclus.latency_GetX_inv : Accumulator : Sum.u64 = 49667175; SumSQ.u64 = 1273342953555; Count.u64 = 2083; Min.u64 = 236; Max.u64 = 41653;
l3cache.msi.inclus.latency_GetX_miss : Accumulator : Sum.u64 = 141689093; SumSQ.u64 = 3623104343407; Count.u64 = 5654; Min.u64 = 1079; Max.u64 = 51058;
l3cache.msi.inclus.latency_GetX_inv : Accumulator : Sum.u64 = 49667177; SumSQ.u64 = 1273343107029; Count.u64 = 2083; Min.u64 = 236; Max.u64 = 41653;
l3cache.msi.inclus.latency_GetX_upgrade : Accumulator : Sum.u64 = 5182699; SumSQ.u64 = 137977642431; Count.u64 = 199; Min.u64 = 12910; Max.u64 = 46594;
l3cache.msi.inclus.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l3cache.msi.inclus.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
Expand Down Expand Up @@ -1274,7 +1274,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr
l3cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
l3cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1;
l3cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 13118; SumSQ.u64 = 13118; Count.u64 = 13118; Min.u64 = 1; Max.u64 = 1;
l3cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 478217663; SumSQ.u64 = 58081101245; Count.u64 = 3955236; Min.u64 = 0; Max.u64 = 128;
l3cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 478217648; SumSQ.u64 = 58081097604; Count.u64 = 3955236; Min.u64 = 0; Max.u64 = 128;
l3cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0;
directory.msi:highlink.packet_latency : Accumulator : Sum.u64 = 3102867; SumSQ.u64 = 350623971; Count.u64 = 27459; Min.u64 = 113; Max.u64 = 113;
directory.msi:highlink.send_bit_count : Accumulator : Sum.u64 = 15714496; SumSQ.u64 = 9045028864; Count.u64 = 27459; Min.u64 = 64; Max.u64 = 576;
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