memH: multiple coherence domains

src/sst/elements/memHierarchy/Makefile.am

@@ -187,6 +187,7 @@ EXTRA_DIST = \
 	tests/testBackendTimingDRAM-3.py \
 	tests/testBackendTimingDRAM-4.py \
 	tests/testBackendVaultSim.py \
+	tests/testCoherenceDomains.py \
 	tests/testCustomCmdGoblin-1.py \
 	tests/testCustomCmdGoblin-2.py \
 	tests/testCustomCmdGoblin-3.py \
@@ -241,6 +242,7 @@ EXTRA_DIST = \
 	tests/refFiles/test_memHA_BackendTimingDRAM_3.out \
 	tests/refFiles/test_memHA_BackendTimingDRAM_4.out \
 	tests/refFiles/test_memHA_BackendVaultSim.out \
+	tests/refFiles/test_memHA_CoherenceDomains.out \
 	tests/refFiles/test_memHA_CustomCmdGoblin_1.out \
 	tests/refFiles/test_memHA_CustomCmdGoblin_2.out \
 	tests/refFiles/test_memHA_CustomCmdGoblin_3.out \

src/sst/elements/memHierarchy/directoryController.cc

@@ -1346,6 +1346,8 @@ bool DirectoryController::handlePutS(MemEvent * event, bool inMSHR) {
         case S_Inv:
             if (mshr->decrementAcksNeeded(addr)) {
                 entry->hasSharers() ? entry->setState(S) : entry->setState(I);
+                retryBuffer.push_back(static_cast<MemEvent*>(mshr->getFrontEvent(addr)));
+                mshr->setInProgress(addr); /* Make sure we don't retry twice */
             }
             break;
         case SD_Inv:

src/sst/elements/memHierarchy/standardInterface.cc

@@ -74,6 +74,17 @@ StandardInterface::StandardInterface(SST::ComponentId_t id, Params &params, Time
 
     baseAddrMask_ = 0;
     lineSize_ = 0;
+
+    std::vector<uint64_t> noncache;
+    params.find_array<uint64_t>("noncacheable_regions", noncache);
+
+    for (int i = 0; i < noncache.size(); i+=2) {
+        MemRegion reg;
+        reg.setEmpty();
+        reg.start = noncache[i];
+        reg.end = noncache[i+1];
+        noncacheableRegions.insert(std::make_pair(reg.start, reg));
+    }
 }
 
 void StandardInterface::setMemoryMappedAddressRegion(Addr start, Addr size) {

src/sst/elements/memHierarchy/standardInterface.h

@@ -78,7 +78,8 @@ class StandardInterface : public Interfaces::StandardMem {
         {"verbose",     "(uint) Output verbosity for warnings/errors. 0[fatal error only], 1[warnings], 2[full state dump on fatal error]", "1"},
         {"debug",       "(uint) Where to send debug output. Options: 0[none], 1[stdout], 2[stderr], 3[file]", "0"},
         {"debug_level", "(uint) Debugging level: 0 to 10. Must configure sst-core with '--enable-debug'. 1=info, 2-10=debug output", "0"},
-        {"port",        "(string) port name to use for interfacing to the memory system. This must be provided if this subcomponent is being loaded anonymously. Otherwise this should not be specified and either the 'port' port should be connected or the 'memlink' subcomponent slot should be filled"}
+        {"port",        "(string) port name to use for interfacing to the memory system. This must be provided if this subcomponent is being loaded anonymously. Otherwise this should not be specified and either the 'port' port should be connected or the 'memlink' subcomponent slot should be filled"},
+        {"noncacheable_regions", "(string) vector of (start, end) address pairs for noncacheable address ranges. Vector format should be [start0, end0, start1, end1, ...].", "[]"}
     )
 
     SST_ELI_DOCUMENT_PORTS( {"port", "Port to memory hierarchy (caches/memory/etc.). Required if subcomponent slot not filled or if 'port' parameter not provided.", {}} )