how to config SPEC2006 in SST to run benchmarks?

[juddyoung]

New Issue for sst-elements

1 - Detailed description of problem or enhancement

2 - Describe how to reproduce

3 - What Operating system(s) and versions

4 - What version of external libraries (Boost, MPI)

5 - Provide sha1 of all relevant sst repositories (sst-core, sst-elements, etc)

6 - Fill out Labels, Milestones, and Assignee fields as best possible

[gvoskuilen]

Are you trying to run this on a specific SST CPU model? Do you have a config file? If not, the simplest method would be to create a python config file for Ariel (or grab one from src/sst/elements/ariel/frontend/simple/examples/stream and point Ariel's 'executable' argument to whatever benchmark you want to run. Use Ariel's 'appargcount' and 'appargX' arguments if you need to give the benchmark input arguments.

[juddyoung]

@gvoskuilen thank you so much, I know how to config now but I met another problem, after running the python configuration file there would be segmentation faults, and I want to config with multi-cores, can you show me how to solve it?
bzip2.txt

[jjwilke]

@juddyoung Is the simulation running and segfaulting at the end? Can you post the output of the backtrace here? Or do you possibly have a gdb backtrace with line numbers?

[juddyoung]

@jjwilke it's running and the segfault does happen at the end.
this is the output after executing "sst bzip2.py"
sst_output.txt
this is the output after "gdb sst" and r "home/juddyoung/mzl/bzip2.py"
gdb_output.txt

[jjwilke]

Can you cut and paste the output directly into the issue tracker? It helps with searching for related issues.

[juddyoung]

@jjwilke ok
this is sst output:

juddyoung@lw:~/mzl$ sst bzip2.py 
Creating Core 0 in Group 0
Creating Core 1 in Group 0
Creating Core 2 in Group 0
Creating Core 3 in Group 0
Creating Core 4 in Group 0
Creating Core 5 in Group 0
Creating Core 6 in Group 0
Creating Core 7 in Group 0
Initialized with 8 cores
Before initialization 
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
After initialization 
[lw:03495] *** Process received signal ***
[lw:03495] Signal: Segmentation fault (11)
[lw:03495] Signal code: Address not mapped (1)
[lw:03495] Failing at address: 0x10
[lw:03495] [ 0] /lib/x86_64-linux-gnu/libpthread.so.0(+0x11390)[0x7f790956e390]
[lw:03495] [ 1] sst(_ZN3SST4Link15recvUntimedDataEv+0x11)[0x4a8d01]
[lw:03495] [ 2] /home/juddyoung/local/sstelements-8.0.0/lib/sst-elements-library/libSamba.so(_ZN3SST14SambaComponent5Samba4initEj+0x53)[0x7f78f97554f3]
[lw:03495] [ 3] sst(_ZN3SST10Simulation10initializeEv+0x64)[0x4b1124]
[lw:03495] [ 4] sst[0x45ce1a]
[lw:03495] [ 5] sst(main+0xee7)[0x450797]
[lw:03495] [ 6] /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xf0)[0x7f790821e830]
[lw:03495] [ 7] sst(_start+0x29)[0x45c869]
[lw:03495] *** End of error message ***
Segmentation fault (core dumped)

this is gdb output:

juddyoung@lw:~/mzl$ gdb /home/juddyoung/local/sstcore-8.0.0/bin/sst
GNU gdb (Ubuntu 7.11.1-0ubuntu1~16.5) 7.11.1
Copyright (C) 2016 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
and "show warranty" for details.
This GDB was configured as "x86_64-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from /home/juddyoung/local/sstcore-8.0.0/bin/sst...done.
(gdb) r /home/juddyoung/mzl/bzip2.py 
Starting program: /home/juddyoung/local/sstcore-8.0.0/bin/sst /home/juddyoung/mzl/bzip2.py
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
process 3525 is executing new program: /home/juddyoung/local/sstcore-8.0.0/libexec/sstsim.x
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
[New Thread 0x7ffff2a71700 (LWP 3529)]
Creating Core 0 in Group 0
Creating Core 1 in Group 0
Creating Core 2 in Group 0
Creating Core 3 in Group 0
Creating Core 4 in Group 0
Creating Core 5 in Group 0
Creating Core 6 in Group 0
Creating Core 7 in Group 0
Initialized with 8 cores
Before initialization 
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
Assigning the PTW correctly
After initialization 

Thread 1 "sstsim.x" received signal SIGSEGV, Segmentation fault.
SST::Link::recvUntimedData (this=0x0) at link.cc:179
179	    if ( untimedQueue == NULL ) return NULL;

[jjwilke]

During initialization (so the simulation hasn't run and completed yet), you're accessing a nullptr link. nullptr links are legal in SST, but in the case of Samba we don't actually intended for any of the links to be null. What's happening is that you're specifying a particular core count with the "corecount" parameter, but then not creating all the necessary links in the python file.

Probably we should have some asserts or error checks in the Samba constructor to make sure the links are non-null. Same with the output, can you directly paste your Python file into the issue instead of posting attachments? It should be easy enough to pick out which links you're missing.

[juddyoung]

@jjwilke

[juddyoung]

@jjwilke

[juddyoung]

@jjwilke

import sst
import os

cores_per_group = 4*2 #2 cores and 2 MMUs
groups = 1
ring_latency = "50ps"

sst.setProgramOption("timebase", "1ps")

ariel_params={
        "verbose": "0",
        "maxcorequeue": "256",
        "maxissuepercycle": "2",
        "pipetimeout": "0",
        "corecount": groups * cores_per_group/2,
        "executable": "/home/juddyoung/spec/cpu2006/benchspec/CPU2006/401.bzip2/exe/bzip2_base.amd64-m64-gcc43-nn",
        "appargcount": 1,
        "apparg0": "/home/juddyoung/spec/cpu2006/benchspec/CPU2006/401.bzip2/data/ref/input/chicken.jpg",
        "arielmode": "1",
        "memmgr.memorylevels": "1",
        "memmgr.defaultlevel": "0"
}

ariel = sst.Component("a0", "ariel.ariel")
ariel.addParams(ariel_params)

l1_params ={
        "cache_frequency" : "2 Ghz",
        "cache_size" : "64 KB",
        "coherence_protocol" : "MSI",
        "replacement_policy" : "lru",
        "associativity" : "8",
        "access_latency_cycles" : "1",
        "cache_line_size" : "64",
        "L1" : "1",
        "debug" : "0"
}

#corecount = 4;

l1cache = sst.Component("l1cache", "memHierarchy.Cache")
l1cache.addParams(l1_params)

memory_params={
        "coherence_protocol": "MSI",
        "backend.access_time": "10ns",
        "backend.mem_size": "2048MiB",
        "clock": "1GHz",
        "use_dramsim": "0",
        "device_ini": "DDR3_micron_32M_8B_x4_sg125.ini",
        "system_ini": "system.ini"
}

memory = sst.Component("memory", "memHierarchy.MemController")
memory.addParams(memory_params)

mmu_params={
        "os_page_size": 4096,
        "corecount": groups * cores_per_group,
        "sizes_L1": 1,
        "page_size1_L1": 4,
        "assoc1_L1": 4,
        "size1_L1": 64,
        "sizes_L2": 1,
        "page_size1_L2": 4,
        "assoc1_L2": 8,
        "size1_L2": 512,
        "clock": "2 Ghz",
        "levels": 2,
        "max_width_L1": 3,
        "max_outstanding_L1": 2,
        "latency_L1": 4,
        "parallel_mode_L1": 1,
        "max_outstanding_L2": 2,
        "max_width_L2": 4,
        "latency_L2": 10,
        "parallel_mode_L2": 0,
        "page_walk_latency": 30,
        "size1_PTWC": 32,  # this just indicates the number entries of the page table walk cache level 1 (PTEs)
        "assoc1_PTWC": 4,  # this just indicates the associtativit the page table walk cache level 1 (PTEs)
        "size2_PTWC": 32,  # this just indicates the number entries of the page table walk cache level 1 (PMDs)
        "assoc2_PTWC": 4,  # this just indicates the associtativit the page table walk cache level 1 (PMDs)
        "size3_PTWC": 32,  # this just indicates the number entries of the page table walk cache level 1 (PUDs)
        "assoc3_PTWC": 4,  # this just indicates the associtativit the page table walk cache level 1 (PUDs)
        "size4_PTWC": 32,  # this just indicates the number entries of the page table walk cache level 1 (PGD)
        "assoc4_PTWC": 4,  # this just indicates the associtativit the page table walk cache level 1 (PGD)
        "latency_PTWC": 10,  # This is the latency of checking the page table walk cache
        "max_outstanding_PTWC": 4
}

mmu = sst.Component("mmu0", "Samba")
mmu.addParams(mmu_params)
for next_group in range(groups):
        for next_active_core in range(cores_per_group):
                print "Creating Core " + str(next_active_core) + " in Group " + str(next_group)

                l1cache = sst.Component("l1cache_" + str(next_core_id), "memHierarchy.Cache")

                l1cache.addParams(l1_params)

                arielMMULink = sst.Link("cpu_mmu_link_" + str(next_core_id))
                MMUCacheLink = sst.Link("mmu_cache_link_" + str(next_core_id))
                PTWMemLink = sst.Link("ptw_mem_link_" + str(next_core_id))

                cpu_mmu_link = sst.Link("cpu_mmu_link0")
                mmu_cache_link = sst.Link("mmu_cache_link")
                memory_link = sst.Link("mem_bus_link")

                if next_core_id < cores_per_group * groups / 2:
                        cpu_mmu_link.connect((ariel, "cache_link_%d" % next_core_id, ring_latency),(mmu, "cpu_to_mmu%d" % next_core_id, ring_latency))
                        mmu_cache_link.connect((mmu, "mmu_to_cache%d" % next_core_id, ring_latency), (l1cache, "high_network_0", ring_latency))
                        memory_link.connect((l1cache, "low_network_%d" % next_core_id, ring_latency),(memory, "direct_link", ring_latency))
                        cpu_mmu_link.setNoCut()
                        mmu_cache_link.setNoCut()
                        memory_link.setNoCut()

                next_core_id = next_core_id + 1

'''
cpu_mmu_link = sst.Link("cpu_mmu_link0")
cpu_mmu_link.connect( (ariel, "cache_link_0", ring_latency), (mmu, "cpu_to_mmu0", ring_latency) )
cpu_mmu_link.setNoCut()

mmu_cache_link = sst.Link("mmu_cache_link")
mmu_cache_link.connect((mmu, "mmu_to_cache0", ring_latency), (l1cache, "high_network_0", ring_latency) )

memory_link = sst.Link("mem_bus_link")
memory_link.connect( (l1cache, "low_network_0", ring_latency), (memory, "direct_link", ring_latency) )
'''

# Set the Statistic Load Level; Statistics with Enable Levels (set in
# elementInfoStatistic) lower or equal to the load can be enabled (default = 0)
sst.setStatisticLoadLevel(5)

# Set the desired Statistic Output (sst.statOutputConsole is default)
#sst.setStatisticOutput("sst.statOutputConsole")
sst.setStatisticOutput("sst.statOutputTXT", {"filepath" : "./TestOutput.txt"  })
#sst.setStatisticOutput("sst.statOutputCSV", {"filepath" : "./TestOutput.csv",
#                                                         "separator" : ", "
#                                            })

# Enable Individual Statistics for the Component with output at end of sim
# Statistic defaults to Accumulator
ariel.enableStatistics([
      "cycles",
      "active_cycles",
      "instruction_count",
      "read_requests",
      "write_requests",
      "total_cores"
])

memory.enableStatistics([
      "total_cycles"
])

l1cache.enableStatistics([
      "CacheHits",
      "CacheMisses"
])

mmu.enableStatistics([
      "tlb_hits",
      "tlb_misses",
      "write_requests",
      "total_waiting"
])

[jjwilke]

@gvoskuilen Not sure if this is based on a template you recognize?

Why are you only creating links for half the cores?

if next_core_id < cores_per_group * groups / 2:

You could also modify the Samba constructor and add asserts for mmu_to_cache[i] and cpu_to_mmu[i] to see which link is null.

[juddyoung]

@jjwilke
import sst
import os

next_core_id = 0
cores_per_group = 2*2 #2 cores and 2 MMUs
groups = 1
ring_latency = "100ps"

sst.setProgramOption("timebase", "1ps")

ariel_params={
"verbose": "0",
"maxcorequeue": "256",
"maxissuepercycle": "2",
"pipetimeout": "0",
"corecount": groups * cores_per_group/2,
"executable": "/home/juddyoung/spec/cpu2006/benchspec/CPU2006/401.bzip2/exe/bzip2_base.amd64-m64-gcc43-nn",
"appargcount": 1,
"apparg0": "/home/juddyoung/spec/cpu2006/benchspec/CPU2006/401.bzip2/data/ref/input/chicken.jpg",
"arielmode": "1",
"memmgr.memorylevels": "1",
"memmgr.defaultlevel": "0"
}

ariel = sst.Component("a0", "ariel.ariel")
ariel.addParams(ariel_params)

l1_params ={
"cache_frequency" : "2 Ghz",
"cache_size" : "64 KB",
"coherence_protocol" : "MSI",
"replacement_policy" : "lru",
"associativity" : "8",
"access_latency_cycles" : "1",
"cache_line_size" : "64",
"L1" : "1",
"debug" : "0"
}

#corecount = 4;

l1cache = sst.Component("l1cache", "memHierarchy.Cache")
l1cache.addParams(l1_params)

memory_params={
"coherence_protocol": "MSI",
"backend.access_time": "10ns",
"backend.mem_size": "2048MiB",
"clock": "1GHz",
"use_dramsim": "0",
"device_ini": "DDR3_micron_32M_8B_x4_sg125.ini",
"system_ini": "system.ini"
}

memory = sst.Component("memory", "memHierarchy.MemController")
memory.addParams(memory_params)

mmu_params={
"os_page_size": 4096,
"corecount": groups * cores_per_group,
"sizes_L1": 1,
"page_size1_L1": 4,
"assoc1_L1": 4,
"size1_L1": 64,
"sizes_L2": 1,
"page_size1_L2": 4,
"assoc1_L2": 8,
"size1_L2": 512,
"clock": "2 Ghz",
"levels": 2,
"max_width_L1": 3,
"max_outstanding_L1": 2,
"latency_L1": 4,
"parallel_mode_L1": 1,
"max_outstanding_L2": 2,
"max_width_L2": 4,
"latency_L2": 10,
"parallel_mode_L2": 0,
"page_walk_latency": 30,
"size1_PTWC": 32, # this just indicates the number entries of the page table walk cache level 1 (PTEs)
"assoc1_PTWC": 4, # this just indicates the associtativit the page table walk cache level 1 (PTEs)
"size2_PTWC": 32, # this just indicates the number entries of the page table walk cache level 1 (PMDs)
"assoc2_PTWC": 4, # this just indicates the associtativit the page table walk cache level 1 (PMDs)
"size3_PTWC": 32, # this just indicates the number entries of the page table walk cache level 1 (PUDs)
"assoc3_PTWC": 4, # this just indicates the associtativit the page table walk cache level 1 (PUDs)
"size4_PTWC": 32, # this just indicates the number entries of the page table walk cache level 1 (PGD)
"assoc4_PTWC": 4, # this just indicates the associtativit the page table walk cache level 1 (PGD)
"latency_PTWC": 10, # This is the latency of checking the page table walk cache
"max_outstanding_PTWC": 4
}

mmu = sst.Component("mmu0", "Samba")
mmu.addParams(mmu_params)

for next_group in range(groups):
for next_active_core in range(cores_per_group):
print "in bzip2.py, Creating Core " + str(next_active_core) + " in Group " + str(next_group)

            cpu_mmu_link = sst.Link("cpu_mmu_link" + str(next_core_id))
            mmu_cache_link = sst.Link("mmu_cache_link" + str(next_core_id))
            memory_link = sst.Link("mem_bus_link" + str(next_core_id))

            if next_core_id < cores_per_group * groups / 2 :
                    cpu_mmu_link.connect((ariel, "cache_link_%d" % next_core_id, ring_latency),(mmu, "cpu_to_mmu%d" % next_core_id, ring_latency))
                    mmu_cache_link.connect((mmu, "mmu_to_cache%d" % next_core_id, ring_latency), (l1cache, "high_network_0", ring_latency))
                    memory_link.connect((l1cache, "low_network_0", ring_latency),(memory, "direct_link", ring_latency))
                    cpu_mmu_link.setNoCut()
                    mmu_cache_link.setNoCut()
                    memory_link.setNoCut()
            next_core_id = next_core_id + 1

Set the Statistic Load Level; Statistics with Enable Levels (set in

elementInfoStatistic) lower or equal to the load can be enabled (default = 0)

sst.setStatisticLoadLevel(5)

Set the desired Statistic Output (sst.statOutputConsole is default)

#sst.setStatisticOutput("sst.statOutputConsole")
sst.setStatisticOutput("sst.statOutputTXT", {"filepath" : "./TestOutput.txt" })
#sst.setStatisticOutput("sst.statOutputCSV", {"filepath" : "./TestOutput.csv",

"separator" : ", "

})

Enable Individual Statistics for the Component with output at end of sim

Statistic defaults to Accumulator

ariel.enableStatistics([
"cycles",
"active_cycles",
"instruction_count",
"read_requests",
"write_requests",
"total_cores"
])

memory.enableStatistics([
"total_cycles"
])

l1cache.enableStatistics([
"CacheHits",
"CacheMisses"
])

mmu.enableStatistics([
"tlb_hits",
"tlb_misses",
"write_requests",
"total_waiting"
])

below is my Samba.cc:

#include <sst_config.h>
#include
#include "Samba.h"

using namespace SST::Interfaces;
using namespace SST;
using namespace SST::SambaComponent;

#define SAMBA_VERBOSE(LEVEL, OUTPUT) if(verbosity >= (LEVEL)) OUTPUT

// Here we do the initialization of the Samba units of the system, connecting them to the cores and instantiating TLB hierachy objects for each one

Samba::Samba(SST::ComponentId_t id, SST::Params& params): Component(id) {

    CR3 = -1;

    core_count = (uint32_t) params.find<uint32_t>("corecount", 1);

    std::cout<<"core_count in Samba.cc:"<<core_count<<std::endl;

    int self = (uint32_t) params.find<uint32_t>("self_connected", 0);

    int emulate_faults = (uint32_t) params.find<uint32_t>("emulate_faults", 0);

    int levels = (uint32_t) params.find<uint32_t>("levels", 1);

    int  page_walk_latency = ((uint32_t) params.find<uint32_t>("page_walk_latency", 50));

    TLB = new TLBhierarchy*[core_count];
    std::cout<<"Initialized with "<<core_count<<" cores in Samba.cc"<<std::endl;


    cpu_to_mmu = (SST::Link **) malloc( sizeof(SST::Link*) * core_count );

    mmu_to_cache = (SST::Link **) malloc( sizeof(SST::Link *) * core_count );

    ptw_to_mem = (SST::Link **) malloc( sizeof(SST::Link *) * core_count );

    ptw_to_opal = (SST::Link **) malloc( sizeof(SST::Link *) * core_count );


    char* link_buffer = (char*) malloc(sizeof(char) * 256);

    char* link_buffer2 = (char*) malloc(sizeof(char) * 256);

    char* link_buffer3 = (char*) malloc(sizeof(char) * 256);

    char* link_buffer4 = (char*) malloc(sizeof(char) * 256);

    std::cout<<"Before initialization "<<std::endl;
    for(uint32_t i = 0; i < core_count; ++i) {

            sprintf(link_buffer, "cpu_to_mmu%" PRIu32, i);

            sprintf(link_buffer2, "mmu_to_cache%" PRIu32, i);



            TLB[i]= new TLBhierarchy(i, levels /* level */, (SST::Component *) this,params);


            SST::Link * link2 = configureLink(link_buffer, "0ps", new Event::Handler<TLBhierarchy>(TLB[i], &TLBhierarchy::handleEvent_CPU));
            if(!link2)
            {
                    cpu_to_mmu[i] = link2;
                    std::cout<<"in Samba.cc constructor, cpu_to_mmu["<<i<<"] is "<<cpu_to_mmu[i]<<std::endl;
            }
            else
                    std::cout<<"in Samba.cc constructor, cpu_to_mmu "<<i<<" is null"<<std::endl;


            SST::Link * link = configureLink(link_buffer2, "0ps", new Event::Handler<TLBhierarchy>(TLB[i], &TLBhierarchy::handleEvent_CACHE));
            if(!link)
            {
                    mmu_to_cache[i] = link;
                    std::cout<<"in Samba.cc constructor, mmu_to_cache["<<i<<"] is "<<mmu_to_cache[i]<<std::endl;
            }
            else
                    std::cout<<"in Samba.cc constructor, mmu_to_cache "<<i<<" is null"<<std::endl;

            sprintf(link_buffer3, "ptw_to_mem%" PRIu32, i);
            SST::Link * link3;

            if(self==0)
                    link3 = configureLink(link_buffer3, "30ps", new Event::Handler<PageTableWalker>(TLB[i]->getPTW(), &PageTableWalker::recvResp));
            else
                    link3 = configureSelfLink(link_buffer3, std::to_string(page_walk_latency)+ "ns", new Event::Handler<PageTableWalker>(TLB[i]->getPTW(), &PageTableWalker::recvResp));

            ptw_to_mem[i] = link3;


            sprintf(link_buffer4, "ptw_to_opal%" PRIu32, i);
            SST::Link * link4;


            if(emulate_faults==1)
            {
                    link4 = configureLink(link_buffer4, "30ps", new Event::Handler<PageTableWalker>(TLB[i]->getPTW(), &PageTableWalker::recvOpal));
                    ptw_to_opal[i] = link4;
                    TLB[i]->setOpalLink(link4);

                    sprintf(link_buffer, "event_bus%" PRIu32, i);

                    event_link = configureSelfLink(link_buffer, "1ns", new Event::Handler<PageTableWalker>(TLB[i]->getPTW(), &PageTableWalker::handleEvent));

                    TLB[i]->getPTW()->setEventChannel(event_link);
                    TLB[i]->setPageTablePointers(&CR3, &PGD, &PUD, &PMD, &PTE, &MAPPED_PAGE_SIZE1GB, &MAPPED_PAGE_SIZE2MB, &MAPPED_PAGE_SIZE4KB);

            }

            TLB[i]->setPTWLink(link3); // We make a connection from the TLB hierarchy to the memory hierarchy, for page table walking purposes
            TLB[i]->setCacheLink(mmu_to_cache[i]);
            TLB[i]->setCPULink(cpu_to_mmu[i]);

    }



    std::cout<<"After initialization "<<std::endl;

    std::string cpu_clock = params.find<std::string>("clock", "1GHz");
    registerClock( cpu_clock, new Clock::Handler<Samba>(this, &Samba::tick ) );



    free(link_buffer);
    free(link_buffer2);
    free(link_buffer3);

}

Samba::Samba() : Component(-1)
{
// for serialization only
//
}

void Samba::init(unsigned int phase) {

    /* 
     * CPU may send init events to memory, pass them through, 
     * also pass memory events to CPU
     */
    std::cout<<"get into Samba.cc's init()"<<std::endl;
    for (uint32_t i = 0; i < core_count; i++) {
            std::cout<<"initializing core "<<i<<std::endl;
            SST::Event * ev;
            while ((ev = cpu_to_mmu[i]->recvInitData())) {
                    //mmu_to_cache[i]->sendInitData(ev);//add by judd
                    if(mmu_to_cache[i])
                    {
                            mmu_to_cache[i]->sendInitData(ev);
                            std::cout<<"in Samba.cc initialization, mmu_to_cache "<<i<<" is "<<mmu_to_cache[i]<<std::endl;
                    }
                    else
                            std::cout<<"in Samba.cc initialization, mmu_to_cache "<<i<<" is null"<<std::endl;
            }

            while ((ev = mmu_to_cache[i]->recvInitData())) {
                    SST::MemHierarchy::MemEventInit * mEv = dynamic_cast<SST::MemHierarchy::MemEventInit*>(ev);
                    if (mEv && mEv->getInitCmd() == SST::MemHierarchy::MemEventInit::InitCommand::Coherence) {
                            SST::MemHierarchy::MemEventInitCoherence * mEvC = static_cast<SST::MemHierarchy::MemEventInitCoherence*>(mEv);
                            TLB[i]->setLineSize(mEvC->getLineSize());
                    }
                    //cpu_to_mmu[i]->sendInitData(ev);//add by judd
                    if(cpu_to_mmu[i])
                    {
                            cpu_to_mmu[i]->sendInitData(ev);
                            std::cout<<"in Samba.cc initialization, cput_to_mmu "<<i<<" is "<<cpu_to_mmu[i]<<std::endl;
                    }
                    else
                            std::cout<<"in Samba.cc initialization, cpu_to_mmu "<<i<<" is null"<<std::endl;
            }
    }

}

bool Samba::tick(SST::Cycle_t x)
{

    // We tick the MMU hierarchy of each core
    for(uint32_t i = 0; i < core_count; ++i)
            TLB[i]->tick(x);


    return false;

}
after executing the code, the result is as below, I can't figure out why the first two cpu_to_mmu[i] and mmu_to_cache[i] are null which cause segfault.

in bzip2.py, Creating Core 0 in Group 0
in bzip2.py, Creating Core 1 in Group 0
in bzip2.py, Creating Core 2 in Group 0
in bzip2.py, Creating Core 3 in Group 0
core_count in Samba.cc:4
Initialized with 4 cores in Samba.cc
Before initialization
Assigning the PTW correctly
in Samba.cc constructor, cpu_to_mmu 0 is null
in Samba.cc constructor, mmu_to_cache 0 is null
Assigning the PTW correctly
in Samba.cc constructor, cpu_to_mmu 1 is null
in Samba.cc constructor, mmu_to_cache 1 is null
Assigning the PTW correctly
in Samba.cc constructor, cpu_to_mmu[2] is 0
in Samba.cc constructor, mmu_to_cache[2] is 0
Assigning the PTW correctly
in Samba.cc constructor, cpu_to_mmu[3] is 0
in Samba.cc constructor, mmu_to_cache[3] is 0
After initialization
get into Samba.cc's init()
initializing core 0
[lw:32078] *** Process received signal ***
[lw:32078] Signal: Segmentation fault (11)
[lw:32078] Signal code: Address not mapped (1)
[lw:32078] Failing at address: 0x30
[lw:32078] [ 0] /lib/x86_64-linux-gnu/libpthread.so.0(+0x11390)[0x7f384aeef390]
[lw:32078] [ 1] sst(_ZN3SST4Link15recvUntimedDataEv+0x1d)[0x4a8d0d]
[lw:32078] [ 2] /home/juddyoung/local/sstelements-8.0.0/lib/sst-elements-library/libSamba.so(_ZN3SST14SambaComponent5Samba4initEj+0x90)[0x7f383b0f05e0]
[lw:32078] [ 3] sst(_ZN3SST10Simulation10initializeEv+0x64)[0x4b1124]
[lw:32078] [ 4] sst[0x45ce1a]
[lw:32078] [ 5] sst(main+0xee7)[0x450797]
[lw:32078] [ 6] /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xf0)[0x7f3849b9f830]
[lw:32078] [ 7] sst(_start+0x29)[0x45c869]
[lw:32078] *** End of error message ***
Segmentation fault (core dumped)