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Merge pull request #10 from spider-tronix/NOR-layout
Nor layout
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.subckt NOR_cell VOUT A B VDD GND | ||
*.iopin VDD | ||
*.iopin GND | ||
*.iopin VOUT | ||
*.iopin B | ||
*.iopin A | ||
XM1 VOUT B GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' | ||
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' | ||
+ sa=0 sb=0 sd=0 mult=1 m=1 | ||
XM2 VOUT A GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' | ||
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' | ||
+ sa=0 sb=0 sd=0 mult=1 m=1 | ||
XM3 VOUT B net1 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' | ||
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' | ||
+ sa=0 sb=0 sd=0 mult=1 m=1 | ||
XM4 net1 A VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' | ||
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' | ||
+ sa=0 sb=0 sd=0 mult=1 m=1 | ||
.ends | ||
** flattened .save nodes | ||
.end |
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v {xschem version=2.9.9 file_version=1.2 } | ||
G {} | ||
K {} | ||
V {} | ||
S {} | ||
E {} | ||
N 2080 -1210 2080 -1150 { lab=VOUT} | ||
N 2080 -1120 2100 -1120 { lab=GND} | ||
N 2100 -1120 2100 -1070 { lab=GND} | ||
N 2080 -1430 2080 -1380 { lab=VDD} | ||
N 2080 -1320 2080 -1270 { lab=#net1} | ||
N 2080 -1350 2100 -1350 { lab=VDD} | ||
N 2100 -1400 2100 -1350 { lab=VDD} | ||
N 2080 -1400 2100 -1400 { lab=VDD} | ||
N 2080 -1240 2100 -1240 { lab=#net1} | ||
N 2100 -1290 2100 -1240 { lab=#net1} | ||
N 2080 -1090 2080 -1040 { lab=GND} | ||
N 2000 -1040 2080 -1040 { lab=GND} | ||
N 2000 -1040 2000 -1010 { lab=GND} | ||
N 1910 -1090 1910 -1040 { lab=GND} | ||
N 1910 -1040 2000 -1040 { lab=GND} | ||
N 2080 -1070 2100 -1070 { lab=GND} | ||
N 1910 -1120 1930 -1120 { lab=GND} | ||
N 1930 -1120 1930 -1070 { lab=GND} | ||
N 1910 -1070 1930 -1070 { lab=GND} | ||
N 1780 -1350 2040 -1350 { lab=A} | ||
N 1780 -1240 2040 -1240 { lab=B} | ||
N 2010 -1120 2040 -1120 { lab=A} | ||
N 2010 -1350 2010 -1120 { lab=A} | ||
N 1840 -1120 1870 -1120 { lab=B} | ||
N 1840 -1240 1840 -1120 { lab=B} | ||
N 1910 -1180 1910 -1150 { lab=VOUT} | ||
N 1910 -1180 2080 -1180 { lab=VOUT} | ||
N 2080 -1180 2160 -1180 { lab=VOUT} | ||
N 2100 -1350 2100 -1290 {} | ||
C {sky130_fd_pr/nfet_01v8.sym} 1890 -1120 0 0 {name=M1 | ||
L=0.15 | ||
W=1 | ||
nf=1 | ||
mult=1 | ||
ad="'int((nf+1)/2) * W/nf * 0.29'" | ||
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" | ||
as="'int((nf+2)/2) * W/nf * 0.29'" | ||
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" | ||
nrd="'0.29 / W'" nrs="'0.29 / W'" | ||
sa=0 sb=0 sd=0 | ||
model=nfet_01v8 | ||
spiceprefix=X | ||
} | ||
C {sky130_fd_pr/nfet_01v8.sym} 2060 -1120 0 0 {name=M2 | ||
L=0.15 | ||
W=1 | ||
nf=1 | ||
mult=1 | ||
ad="'int((nf+1)/2) * W/nf * 0.29'" | ||
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" | ||
as="'int((nf+2)/2) * W/nf * 0.29'" | ||
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" | ||
nrd="'0.29 / W'" nrs="'0.29 / W'" | ||
sa=0 sb=0 sd=0 | ||
model=nfet_01v8 | ||
spiceprefix=X | ||
} | ||
C {sky130_fd_pr/pfet_01v8.sym} 2060 -1240 0 0 {name=M3 | ||
L=0.15 | ||
W=1 | ||
nf=1 | ||
mult=1 | ||
ad="'int((nf+1)/2) * W/nf * 0.29'" | ||
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" | ||
as="'int((nf+2)/2) * W/nf * 0.29'" | ||
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" | ||
nrd="'0.29 / W'" nrs="'0.29 / W'" | ||
sa=0 sb=0 sd=0 | ||
model=pfet_01v8 | ||
spiceprefix=X | ||
} | ||
C {sky130_fd_pr/pfet_01v8.sym} 2060 -1350 0 0 {name=M4 | ||
L=0.15 | ||
W=1 | ||
nf=1 | ||
mult=1 | ||
ad="'int((nf+1)/2) * W/nf * 0.29'" | ||
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'" | ||
as="'int((nf+2)/2) * W/nf * 0.29'" | ||
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'" | ||
nrd="'0.29 / W'" nrs="'0.29 / W'" | ||
sa=0 sb=0 sd=0 | ||
model=pfet_01v8 | ||
spiceprefix=X | ||
} | ||
C {devices/iopin.sym} 2080 -1430 3 0 {name=p1 lab=VDD} | ||
C {devices/iopin.sym} 2000 -1010 1 0 {name=p2 lab=GND} | ||
C {devices/iopin.sym} 2160 -1180 0 0 {name=p3 lab=VOUT} | ||
C {devices/iopin.sym} 1780 -1240 0 1 {name=p4 lab=B} | ||
C {devices/iopin.sym} 1780 -1350 0 1 {name=p5 lab=A} |
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Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 has no definition, treated as a black box. | ||
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 has no definition, treated as a black box. | ||
|
||
Subcircuit pins: | ||
Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8 | ||
-------------------------------------------|------------------------------------------- | ||
1 |1 | ||
2 |2 | ||
3 |3 | ||
4 |4 | ||
--------------------------------------------------------------------------------------- | ||
Cell pin lists are equivalent. | ||
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent. | ||
Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 has no definition, treated as a black box. | ||
Warning: Equate pins: cell sky130_fd_pr__pfet_01v8 has no definition, treated as a black box. | ||
|
||
Subcircuit pins: | ||
Circuit 1: sky130_fd_pr__pfet_01v8 |Circuit 2: sky130_fd_pr__pfet_01v8 | ||
-------------------------------------------|------------------------------------------- | ||
1 |1 | ||
2 |2 | ||
3 |3 | ||
4 |4 | ||
--------------------------------------------------------------------------------------- | ||
Cell pin lists are equivalent. | ||
Device classes sky130_fd_pr__pfet_01v8 and sky130_fd_pr__pfet_01v8 are equivalent. | ||
|
||
Subcircuit summary: | ||
Circuit 1: NOR_cell |Circuit 2: nor_layout | ||
-------------------------------------------|------------------------------------------- | ||
sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2) | ||
sky130_fd_pr__pfet_01v8 (2) |sky130_fd_pr__pfet_01v8 (2) | ||
Number of devices: 4 |Number of devices: 4 | ||
Number of nets: 6 |Number of nets: 6 | ||
--------------------------------------------------------------------------------------- | ||
Circuits match uniquely. | ||
Property errors were found. | ||
Netlists match uniquely. | ||
There were property errors. | ||
sky130_fd_pr__pfet_01v8M3 vs. sky130_fd_pr__pfet_01v80: | ||
Property mult in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M3 vs. sky130_fd_pr__pfet_01v80: | ||
Property sd in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M3 vs. sky130_fd_pr__pfet_01v80: | ||
Property sb in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M3 vs. sky130_fd_pr__pfet_01v80: | ||
Property sa in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M3 vs. sky130_fd_pr__pfet_01v80: | ||
Property nrs in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M3 vs. sky130_fd_pr__pfet_01v80: | ||
Property nrd in circuit1 has no matching property in circuit2 | ||
ps circuit1: (unresolved expression) "0" (property type mismatch) | ||
pd circuit1: (unresolved expression) "0" (property type mismatch) | ||
as circuit1: (unresolved expression) "0" (property type mismatch) | ||
ad circuit1: (unresolved expression) "0" (property type mismatch) | ||
sky130_fd_pr__pfet_01v8M3 vs. sky130_fd_pr__pfet_01v80: | ||
Property nf in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M4 vs. sky130_fd_pr__pfet_01v83: | ||
Property mult in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M4 vs. sky130_fd_pr__pfet_01v83: | ||
Property sd in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M4 vs. sky130_fd_pr__pfet_01v83: | ||
Property sb in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M4 vs. sky130_fd_pr__pfet_01v83: | ||
Property sa in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M4 vs. sky130_fd_pr__pfet_01v83: | ||
Property nrs in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__pfet_01v8M4 vs. sky130_fd_pr__pfet_01v83: | ||
Property nrd in circuit1 has no matching property in circuit2 | ||
ps circuit1: (unresolved expression) "0" (property type mismatch) | ||
pd circuit1: (unresolved expression) "0" (property type mismatch) | ||
as circuit1: (unresolved expression) "0" (property type mismatch) | ||
ad circuit1: (unresolved expression) "0" (property type mismatch) | ||
sky130_fd_pr__pfet_01v8M4 vs. sky130_fd_pr__pfet_01v83: | ||
Property nf in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M2 vs. sky130_fd_pr__nfet_01v82: | ||
Property mult in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M2 vs. sky130_fd_pr__nfet_01v82: | ||
Property sd in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M2 vs. sky130_fd_pr__nfet_01v82: | ||
Property sb in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M2 vs. sky130_fd_pr__nfet_01v82: | ||
Property sa in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M2 vs. sky130_fd_pr__nfet_01v82: | ||
Property nrs in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M2 vs. sky130_fd_pr__nfet_01v82: | ||
Property nrd in circuit1 has no matching property in circuit2 | ||
ps circuit1: (unresolved expression) "0" (property type mismatch) | ||
pd circuit1: (unresolved expression) "0" (property type mismatch) | ||
as circuit1: (unresolved expression) "0" (property type mismatch) | ||
ad circuit1: (unresolved expression) "0" (property type mismatch) | ||
sky130_fd_pr__nfet_01v8M2 vs. sky130_fd_pr__nfet_01v82: | ||
Property nf in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M1 vs. sky130_fd_pr__nfet_01v81: | ||
Property mult in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M1 vs. sky130_fd_pr__nfet_01v81: | ||
Property sd in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M1 vs. sky130_fd_pr__nfet_01v81: | ||
Property sb in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M1 vs. sky130_fd_pr__nfet_01v81: | ||
Property sa in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M1 vs. sky130_fd_pr__nfet_01v81: | ||
Property nrs in circuit1 has no matching property in circuit2 | ||
sky130_fd_pr__nfet_01v8M1 vs. sky130_fd_pr__nfet_01v81: | ||
Property nrd in circuit1 has no matching property in circuit2 | ||
ps circuit1: (unresolved expression) "0" (property type mismatch) | ||
pd circuit1: (unresolved expression) "0" (property type mismatch) | ||
as circuit1: (unresolved expression) "0" (property type mismatch) | ||
ad circuit1: (unresolved expression) "0" (property type mismatch) | ||
sky130_fd_pr__nfet_01v8M1 vs. sky130_fd_pr__nfet_01v81: | ||
Property nf in circuit1 has no matching property in circuit2 | ||
|
||
Subcircuit pins: | ||
Circuit 1: NOR_cell |Circuit 2: nor_layout | ||
-------------------------------------------|------------------------------------------- | ||
GND |GND | ||
B |B | ||
A |A | ||
VOUT |VOUT | ||
VDD |VDD | ||
--------------------------------------------------------------------------------------- | ||
Cell pin lists are equivalent. | ||
Device classes NOR_cell and nor_layout are equivalent. | ||
Circuits match uniquely. | ||
Property errors were found. | ||
The following cells had property errors: NOR_cell |
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timestamp 1634664404 | ||
version 8.3 | ||
tech sky130A | ||
style ngspice() | ||
scale 1000 1 500000 | ||
resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 | ||
parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd | ||
parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd | ||
port "VOUT" 1 -360 270 -360 270 m1 | ||
port "B" 3 620 270 620 270 li | ||
port "A" 2 620 630 620 630 li | ||
port "VDD" 4 50 610 50 610 m1 | ||
port "GND" 5 -20 -90 -20 -90 m1 | ||
node "VOUT" 1366 1306.6 -360 270 m1 0 0 0 0 0 0 0 0 40000 1200 20000 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43200 1560 86800 2900 0 0 0 0 0 0 0 0 0 0 | ||
node "a_180_310#" 788 0 180 310 pdif 0 0 0 0 0 0 0 0 0 0 10000 500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
node "B" 1335 463.735 620 270 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28900 1820 0 0 10400 520 0 0 0 0 0 0 0 0 0 0 0 0 | ||
node "A" 2089 759.6 620 630 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43000 2760 0 0 10400 520 0 0 0 0 0 0 0 0 0 0 0 0 | ||
node "VDD" 3621 537.527 50 610 m1 0 0 0 0 137200 1540 0 0 20000 600 20000 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32400 720 49400 920 0 0 0 0 0 0 0 0 0 0 | ||
substrate "GND" 0 0 -20 -90 m1 0 0 0 0 0 0 0 0 40000 1200 40000 1200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64800 1440 83300 2480 0 0 0 0 0 0 0 0 0 0 | ||
cap "VOUT" "VDD" 382.468 | ||
cap "VOUT" "A" 125.2 | ||
cap "VOUT" "B" 55.85 | ||
cap "A" "B" 109.745 | ||
device msubckt sky130_fd_pr__nfet_01v8 230 0 231 1 l=30 w=200 "GND" "B" 60 0 "GND" 200 0 "VOUT" 200 0 | ||
device msubckt sky130_fd_pr__nfet_01v8 -160 0 -159 1 l=30 w=200 "GND" "A" 60 0 "GND" 200 0 "VOUT" 200 0 | ||
device msubckt sky130_fd_pr__pfet_01v8 230 310 231 311 l=30 w=200 "VDD" "B" 60 0 "a_180_310#" 200 0 "VOUT" 200 0 | ||
device msubckt sky130_fd_pr__pfet_01v8 150 310 151 311 l=30 w=200 "VDD" "A" 60 0 "VDD" 200 0 "a_180_310#" 200 0 | ||
subcap "VOUT" -1077.44 |
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