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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/…
…benh/powerpc Pull powerpc update from Benjamin Herrenschmidt: "The main highlights this time around are: - A pile of addition POWER8 bits and nits, such as updated performance counter support (Michael Ellerman), new branch history buffer support (Anshuman Khandual), base support for the new PCI host bridge when not using the hypervisor (Gavin Shan) and other random related bits and fixes from various contributors. - Some rework of our page table format by Aneesh Kumar which fixes a thing or two and paves the way for THP support. THP itself will not make it this time around however. - More Freescale updates, including Altivec support on the new e6500 cores, new PCI controller support, and a pile of new boards support and updates. - The usual batch of trivial cleanups & fixes" * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (156 commits) powerpc: Fix build error for book3e powerpc: Context switch the new EBB SPRs powerpc: Turn on the EBB H/FSCR bits powerpc: Replace CPU_FTR_BCTAR with CPU_FTR_ARCH_207S powerpc: Setup BHRB instructions facility in HFSCR for POWER8 powerpc: Fix interrupt range check on debug exception powerpc: Update tlbie/tlbiel as per ISA doc powerpc: Print page size info during boot powerpc: print both base and actual page size on hash failure powerpc: Fix hpte_decode to use the correct decoding for page sizes powerpc: Decode the pte-lp-encoding bits correctly. powerpc: Use encode avpn where we need only avpn values powerpc: Reduce PTE table memory wastage powerpc: Move the pte free routines from common header powerpc: Reduce the PTE_INDEX_SIZE powerpc: Switch 16GB and 16MB explicit hugepages to a different page table format powerpc: New hugepage directory format powerpc: Don't truncate pgd_index wrongly powerpc: Don't hard code the size of pte page powerpc: Save DAR and DSISR in pt_regs on MCE ...
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=================================================================== | ||
Power Architecture CPU Binding | ||
Copyright 2013 Freescale Semiconductor Inc. | ||
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Power Architecture CPUs in Freescale SOCs are represented in device trees as | ||
per the definition in ePAPR. | ||
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In addition to the ePAPR definitions, the properties defined below may be | ||
present on CPU nodes. | ||
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PROPERTIES | ||
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- fsl,eref-* | ||
Usage: optional | ||
Value type: <empty> | ||
Definition: The EREF (EREF: A Programmer.s Reference Manual for | ||
Freescale Power Architecture) defines the architecture for Freescale | ||
Power CPUs. The EREF defines some architecture categories not defined | ||
by the Power ISA. For these EREF-specific categories, the existence of | ||
a property named fsl,eref-[CAT], where [CAT] is the abbreviated category | ||
name with all uppercase letters converted to lowercase, indicates that | ||
the category is supported by the implementation. |
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