duo 256m system dma no IRQ

[stavinsky]

I'm trying to implement i2s driver by my own.
Ive described regmap for most of registers. And I was able to start tdm2. I see expected lrclk and bclk on oscilloscope.
clocks are fine.
Ive also hardcoded for now recommendations for i2s2 from some vendor file

0x03009804[0] = 1'b1 (rg_ephy_apb_rw_sel=1, use apb interface)
0x03009808[4:0] = 5'b00001 (rg_ephy_pll_stable_cnt[4:0] = 5'd1 (10us)
0x03009800[2] = 0x0905 (rg_ephy_dig_rst_n=1, reset release, other keep default)
wait 10us
0x0300907C[12:8]= 5'b00101 (page_sel_mode0 = page 5)
0x03009078[11:0] = 0xF00 (set to gpio from top)
0x03009074[10:9 2:1]= 0x606 (set ephy rxp&rxm input&output enable)
0x03009070[10:9 2:1]= 0x606 (set ephy rxp&rxm input&output enable)

so I2s starts
I'm not sure about dma channels. I chose 4 and 5 according to trm document.
the problem is that I don't see any interrupts in /proc/interrupts
but I see unhandled interrupt from DMAC_INTSTATUSREG

devmem 0x04330030 32

0x00000001

So I'm missing something connected to System DMA and interrupts.

# cat /proc/interrupts  | grep dw_axi_dmac_platform
 12:          0 SiFive PLIC  29 Level     dw_axi_dmac_platform

dmesg shows me that on aplay -D hw:0,0 -f S24_LE -c 2 -r 48000 /dev/zero

[   36.055940] dw_axi_dmac_platform 4330000.dma-controller: apb_regs not initialized                    
[   36.063718] sg2002-i2s 4120000.i2s: tx start                                                         
[   36.642941] sg2002-i2s 4120000.i2s: tx stop                                                          
[   36.647323] dw_axi_dmac_platform 4330000.dma-controller: apb_regs not initialized  

# devmem 0x04330030 32 
0x00000001

here is my device tree.

&i2s2 {
	pinctrl-0 = <&i2s2_cfg>;
	pinctrl-names = "default";
	#sound-dai-cells = <0>;
	dmas = <&dmamux 4 0>,
	<&dmamux 5 0>;
	dma-names = "rx", "tx";
	capability = "txrx";
	mclk_out = "false";// todo: ignored for the moment
	clocks = <&clk CLK_APB_I2S2>,  <&clk CLK_SDMA_AUD2>;
	clock-names = "i2s", "mclk";
	status = "okay";
	aiao = <&aiao>;
	aiao,tdm-id = <2>;
	assigned-clocks = <&clk CLK_SDMA_AUD2>;
	assigned-clock-rates = <49152000>;   /* 12.288 MHz requested */
	
	#sound-dai-cells = <0>;
};
/ {
	codec0: dummy-codec {
		compatible = "sg2002,dummy-codec";
		#sound-dai-cells = <0>;
	};
	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "sg2002-i2s";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sound_cpu>;
		simple-audio-card,frame-master = <&sound_cpu>;
		sound_cpu: simple-audio-card,cpu {
			sound-dai = <&i2s2>;
		};
		simple-audio-card,codec {
			sound-dai = <&codec0>;// real codec node, or whatever you have
		};
	};
};

[stavinsky]

sorry Ive posted this before read the instructions about submitting issue. If this is not related to the repo, please close the issue.

[inochisa]

Oh, this is fine for here. It is good to have some discussion before submitting patches.

[inochisa]

@stavinsky Have you tried DMA self test module in the liunx kernel? This will give you some information about the state of DMA controller

[stavinsky]

Im not sure Ive done this correctly but i'm getting timeouts. From my understanding PLIC module doesn't receive any interrupts from system dma (by system dma i mean the dma working with peripherals )
So right now I see interrupt in status register and nothing in /proc/interrupts.
basically I have two questions:

1. is there any layer between system dma irq and plic?
2. did I choose dma channels correctly? (4 and 5 for tdm2)

[inochisa]

Im not sure Ive done this correctly but i'm getting timeouts. From my understanding PLIC module doesn't receive any interrupts from system dma (by system dma i mean the dma working with peripherals ) So right now I see interrupt in status register and nothing in /proc/interrupts. basically I have two questions:

1. is there any layer between system dma irq and plic?

IIRC, nothing

2. did I choose dma channels correctly? (4 and 5 for tdm2)

I think it does not matter, the number are assigned dynamicly. In fact, I'm not sure whether it is worked, as the document I got is completely a mess....

[inochisa]

2. did I choose dma channels correctly? (4 and 5 for tdm2)

I think your configuration does not match upstream bindings

https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/dma/sophgo,cv1800b-dmamux.yaml

[stavinsky]

Almost a week of my days off I've spent on this problem.
It was so obvious but still so hidden.
RISC CPU is the CPU1, not CPU0

[stavinsky]

hope you can help me here, @inochisa
in this code: https://github.com/sophgo/linux/blob/for-next/drivers/dma/cv1800b-dmamux.c#L208-L221
you are creating list of channels, adding everytime after head
head -> 0
head -> 1 0
...
head -> 7 6 5 4 3 2 1 0

so the first consumed channel will be 7.
but dwc2 driver starts from 0 so it will use channel 0 first
From my perspective it is a mistake. And in my code I reversed this order, but if not sure if it is correct and how it will work with multiple channels.

why it is a potential problem:
for the following DT snippet

	dmas = <&dmamux 4 1>,
	<&dmamux 5 1>;
	dma-names = "rx", "tx";

dwc2 will use channel 0 and 1 as the first available ones
in sdma_dma_int_mux channel 7 and 6 will be connected to cpu, instead of 0 and 1. No interrupt will be received
in sdma_dma_ch_remap0 and sdma_dma_ch_remap1 7 and 6 will be remapped to desired peripheral

[stavinsky]

the driver works fine for me. Im preparing the series of patches for the review.
the patch for dmamux was sent to lkml.
The issue can be closed I think. Thanks @inochisa for the help.

[inochisa]

the driver works fine for me. Im preparing the series of patches for the review.

Good Work

the patch for dmamux was sent to lkml. The issue can be closed I think. Thanks @inochisa for the help.

The DMA controller is "snps,axi-dma-1.01a", which supports setting channel with any id. I feel weird about using the channel 0 first. I will leave this issue opened for further discussion.

[inochisa]

@stavinsky Does you mean the driver dwc2 is dw-axi-dmac-platform?

[stavinsky]

@inochisa yep. My bad, it is typo. I'm using default DT from this repo if possible.

To be honest I aslo don't understand how it works and it feels strange, because I also believe it should work with any ID. But when in dma mux we taking 7th channel first, correct field is updated update_dma_remp_4_7 (see trm document ) also reg_dma_int_mux_cpu1 is getting correct bit (don't remember 7 or 8 but that part works for me).
but when I start actual transaction, i'm don't receive IRQ.
while investigating this I figured out that dma0 was used by DMA registers state (where was a pending interrupt from dma0)

When I've tried to reverse order as in patch everything got ok and I was able to listen to microphone and playback audio via i2s2

I've also checked multiple channels (i started 2 tdm's simultaneously ) it also works.
I will prepare a driver in a few days so you will be able to play with it if you want.

[inochisa]

I suspect it is caused by
https://github.com/torvalds/linux/blob/master/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c#L1360-L1374

This means the driver always select channel 0 for the first allocation, instead of for a specific channel.