100DaysOfRTL

Toolchain:

• iverilog for simulation
• yosys for synthesis
• make for managing the infra

Table of contents

Days 1-25	Days 25-50	Days 51-75	Days 76-100
Day 1: RTL Mux	Day 26 - TB Constraints	Day 51 - Formal proofs for APB Master	Day 76 - UVM TB for APB Master - 4
Day 2: RTL Dff with asynchronous reset	Day 27 - TB Queues	Day 52 - Formal APB Slave	Day 77 - UVM TB for APB Master - 5
Day 3: RTL Edge detector	Day 28 - TB Associative Array	Day 53 - Formal APB Slave 2	Day 78 - Single Cycle RISC-V
Day 4: RTL ALU	Day 29 - TB Events	Day 54 - Formal APB Slave 3	Day 79 - Single Cycle RISC-V
Day 5: RTL Odd counter	Day 30 - TB Mailbox	Day 55 - Formal Fifo	Day 80 - Single Cycle RISC-V
Day 6: RTL Shift register	Day 31 - TB Function vs Tasks	Day 56 - UVM: Hello World 1	Day 81 - Single Cycle RISC-V
Day 7: RTL LFSR	Day 32 - TB Clocking blocks	Day 57 - UVM: Analysis Port	Day 82 - Single Cycle RISC-V
Day 8: RTL Binary to one hot converter	Day 33 - TB Fork and join	Day 58 - UVM: Driver/Sequencer Communication	Day 83 - Single Cycle RISC-V
Day 9: RTL Binary to Gray converter	Day 34 - TB Fork and join_any	Day 59 - UVM: Driver/Sequencer Communication	Day 84 - Single Cycle RISC-V
Day 10: RTL Self Reloading Counter	Day 35 - TB Fork and join_none	Day 60 - UVM: Driver/Sequencer Communication	Day 85 - Single Cycle RISC-V
Day 11: RTL Parallel to serial shifter	Day 36 - TB Disable Fork	Day 61 - UVM TB for APB Master - 1	Day 86 - Single Cycle RISC-V
Day 12: RTL Sequence detector	Day 37 - TB Wait Fork	Day 62 - UVM TB for APB Slave - 2	Day 87 - Single Cycle RISC-V
Day 13 : RTL Ways to implement Mux	Day 38 - TB Automatic Variables	Day 63 - UVM TB for APB Slave - 3	Day 88 - Single Cycle RISC-V
Day 14 - RTL Fixed Priority Arbiter	Day 39 - TB DPI Calls	Day 64 - Happy Independence Day	Day 89 - Single Cycle RISC-V
Day 15 - RTL Round Robin Arbiter	Day 40 - TB Mux	Day 65 - UVM TB for APB Slave - 4	Day 90 - Single Cycle RISC-V
Day 16 - RTL APB Master	Day 41 - TB ALU	Day 66 - UVM TB for APB Slave - 5	Day 91 - Single Cycle RISC-V
Day 17 - RTL Simple Memory Interface	Day 42 - TB Fixed Priority Arbiter	Day 67 - UVM TB for APB Slave - 6	Day 92 - Single Cycle RISC-V
Day 18 - RTL APB Slave	Day 43 - TB DFF	Day 68 - UVM TB for APB Slave - 7	Day 93 - Single Cycle RISC-V
Day19	Day 44 - TB Parameterised Class	Day 69 - UVM TB for APB Slave - 8	Day 94 - Single Cycle RISC-V
Day 20 - RTL APB System	Day 45 - TB Self reloading counter	Day 70 - UVM TB for APB Slave - 9	Day 95 - Single Cycle RISC-V
Day 21 - TB Introduction	Day 46 - Formal Mux	Day 71 - UVM TB for APB Slave - 10	Day 96 - Single Cycle RISC-V
Day 22 - TB Hello World using SV Classes	Day 47 - Formal ALU	Day 72 - UVM TB for APB Slave - 11	Day 97 - Single Cycle RISC-V
Day 23 - TB Interfaces	Day 48 - Formal DFF	Day 73 - UVM TB for APB Master - 1	Day 98 - Single Cycle RISC-V
Day 24 - TB Virtual Interfaces	Day 49 - Formal Self reloading counter	Day 74 - UVM TB for APB Master - 2	Day 99 - Single Cycle RISC-V
Day 25 - TB Randomize()	Day 50 - Formal Fixed Priority Arbiter	Day 75 - UVM TB for APB Master - 3	Day100 - #100DaysofRTL