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1. LDO_DESIGN_7nm_FinFET LDO_DESIGN_7nm_FinFET Public

   Custom LDO design in a 7nm FinFET process: two-stage OTA error amplifier driving a PMOS pass transistor, with feedforward capacitor compensation. Achieves 72.75° phase margin, 15.18 dB gain margin,…

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2. Limited-Data-Benchmark-Adaptation-for-Lithography-Hotspot-Detection Limited-Data-Benchmark-Adaptation-for-Lithography-Hotspot-Detection Public

   This work investigates whether a convolutional neural network (CNN) pretrained on one ICCAD-12 benchmark (source) can be adapted to a different benchmark (target) using only a small fraction.

   Jupyter Notebook

3. TSMC7nm-TwoStage-OpAmp TSMC7nm-TwoStage-OpAmp Public

   Fully characterized two-stage OTA designed and simulated in Cadence Virtuoso using Spectre. All analyses were run at the schematic level. Desgined to function as an error amplifier for LDO.

4. Dynamic-Memory-Configuration-and-Reconfiguration-on-FPGA Dynamic-Memory-Configuration-and-Reconfiguration-on-FPGA Public

   This project implements a fully hardware-based dynamic DDR memory allocator in SystemVerilog. The allocator divides DDR memory into independent regions — one per hardware component — each backed b…

   SystemVerilog 2

5. JLFET-vs-CIGAAFET JLFET-vs-CIGAAFET Public

   Sentaurus TCAD simulation study of 8 nm nanowire Gate-All-Around FETs in Core-Insulator GAAFET (CIGAAFET) configuration along with JUNCTIONLESS FET. Course project for BEVD206L Semiconductor Devic…

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6. bjt-thermal-sensing-cadence bjt-thermal-sensing-cadence Public

   BJT-based PTAT thermal sensing circuit with adaptive biasing — designed and simulated in Cadence Virtuoso

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