Collect some CS textbooks for learning.

A paper list of some recent works about Token Compress for Vit and VLM

The official implementation of the AAAI 2024 paper Bi-ViT.

⭐⭐⭐ Pytorch implementation of Attentiom, Backbone, ViT, MLP, Re-parameter, Convolution, very flexible module combination.

HSI常用数据集/高光谱图像

A slim implementation of Self-Pooling Transformer for hyperspectral image classification.

A Survey on Transformer in CV.

An comprehensive list of hyperspectral image classification resources (papers & codes & related websites) collected by Jiaqi Zou (immortal@whu.edu.cn)

Explore visualization tools for understanding Transformer-based large language models (LLMs)

The codebase for paper "PPT: Token Pruning and Pooling for Efficient Vision Transformer"

An awesome repository & A comprehensive survey on interpretability of LLM attention heads.

🍀 Pytorch implementation of various Attention Mechanisms, MLP, Re-parameter, Convolution, which is helpful to further understand papers.⭐⭐⭐

Code repo for the paper BiT Robustly Binarized Multi-distilled Transformer

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

μNAS is a neural architecture search (NAS) system that designs small-yet-powerful microcontroller-compatible neural networks.

MicroNAS: Memory and Latency Constrained Hardware-Aware Neural Architecture Search for Time Series Classification on Microcontrollers

Searching for Hardware Aware Neural Networks on ImageNet for FPGA in MobilenetV3 Search Space

Environment Sound Classification with Deep Learning using Hardware Aware - Neural Architecture Search

This is a repo of Hardware-aware training for LSTM

Harmonic-NAS: Hardware-Aware Multimodal Neural Architecture Search on Resource-constrained Devices (ACML 2023)

This is a collection of our research on efficient AI, covering hardware-aware NAS and model compression.

Curated content for DNN approximation, acceleration ... with a focus on hardware accelerator and deployment

This is the Arduino® compatible port of the AIfES machine learning framework, developed and maintained by Fraunhofer Institute for Microelectronic Circuits and Systems.

Demonstrate on-device training of a neural network using AIfES Library on an ESP32 board, learning the XOR gate function.

simple neural network library in ANSI C