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Adding bidirectional IO cells #60
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Shouldn't these be added to: https://github.com/siliconcompiler/lambdalib/blob/6e1a80c592c1f5ac8d456274a75609f8d119c802/lambdalib/padring/rtl/la_iopadring.vh lambdalib/lambdalib/padring/rtl/la_ioside.v Line 227 in 6e1a80c
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LGTM, juts fix the typos and add the cells to the padring files so they can be instantiated from there.
- Consistent with previous naming methodology for iolib
- Needed to be able to support proper rx differential cells that allow for pseudo differential low skew digital signals to be sent to the core.
Updated header file and added support for differential digital RX signals at padring interface. |
.RINGW(RINGW) | ||
) i0 ( // pad | ||
.padp(pad[CELLMAP[(i*24+8)+:8]]), | ||
.padn(pad[i+1]), //TODO: fix! |
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what's with this todo?
.RINGW(RINGW) | ||
) i0 ( // pad | ||
.padp(pad[CELLMAP[(i*24+8)+:8]]), | ||
.padn(pad[i+1]), //TODO: fix! |
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same
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What is the plan with the port connections listed as TODO?
The differential signal indexing is not implemented yet. I copy pasted it from the xtal cell which has never been tested. I will merge this and fix bug later. |
@aolofsson alright, can you create an issue for it so we can keep track of it? |
done |
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