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Adding bidirectional IO cells #60

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Merged
merged 4 commits into from
Jul 16, 2024
Merged

Adding bidirectional IO cells #60

merged 4 commits into from
Jul 16, 2024

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aolofsson
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@aolofsson aolofsson requested a review from gadfort July 16, 2024 18:23
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gadfort commented Jul 16, 2024

Shouldn't these be added to: https://github.com/siliconcompiler/lambdalib/blob/6e1a80c592c1f5ac8d456274a75609f8d119c802/lambdalib/padring/rtl/la_iopadring.vh
and
here:

else if (CELLMAP[i*24+:4] == LA_VSSA[3:0]) begin : ila_iovssa

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LGTM, juts fix the typos and add the cells to the padring files so they can be instantiated from there.

- Consistent with previous naming methodology for iolib
- Needed to be able to support proper rx differential cells that allow for pseudo differential low skew digital signals to be sent to the core.
@aolofsson aolofsson requested a review from gadfort July 16, 2024 19:14
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Updated header file and added support for differential digital RX signals at padring interface.

.RINGW(RINGW)
) i0 ( // pad
.padp(pad[CELLMAP[(i*24+8)+:8]]),
.padn(pad[i+1]), //TODO: fix!
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what's with this todo?

.RINGW(RINGW)
) i0 ( // pad
.padp(pad[CELLMAP[(i*24+8)+:8]]),
.padn(pad[i+1]), //TODO: fix!
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same

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What is the plan with the port connections listed as TODO?

@aolofsson
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What is the plan with the port connections listed as TODO?

The differential signal indexing is not implemented yet. I copy pasted it from the xtal cell which has never been tested. I will merge this and fix bug later.

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gadfort commented Jul 16, 2024

@aolofsson alright, can you create an issue for it so we can keep track of it?

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done

@aolofsson aolofsson merged commit f39a0cd into main Jul 16, 2024
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@aolofsson aolofsson deleted the diff_io branch July 16, 2024 19:28
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2 participants