CA_CA4

Pipe Line Processor design with verilog

Name		Name	Last commit message	Last commit date
Latest commit History 47 Commits
memoryFile		memoryFile
work		work
ALU.v		ALU.v
EX&MEM.v		EX&MEM.v
EX.v		EX.v
HazardUnit.v		HazardUnit.v
HazardUnit.v.bak		HazardUnit.v.bak
ID&EX.v		ID&EX.v
ID.v		ID.v
IF&ID.v		IF&ID.v
IF.v		IF.v
InstMem.v		InstMem.v
MEMandWB.v		MEMandWB.v
MUX32.v		MUX32.v
MUX32in3.v		MUX32in3.v
MUX5.v		MUX5.v
Memory.v		Memory.v
PC.v		PC.v
README.md		README.md
RegFile.v		RegFile.v
Shift2b26.v		Shift2b26.v
Shift2b32.v		Shift2b32.v
SignExt.v		SignExt.v
TB.v		TB.v
TB.v.bak		TB.v.bak
WB.v		WB.v
ca4.cr.mti		ca4.cr.mti
ca4.mpf		ca4.mpf
controlUnit.v		controlUnit.v
controlUnit.v.bak		controlUnit.v.bak
data.hex		data.hex
forwarding.v		forwarding.v
instructions.hex		instructions.hex
pipelineMIPS.v		pipelineMIPS.v
pipelineMIPS.v.bak		pipelineMIPS.v.bak
vsim.wlf		vsim.wlf

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