Fixed missing *passed/*failed assignments.

shariethernet · Mar 17, 2020 · fe372e7 · fe372e7
1 parent 8a66931
commit fe372e7
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Showing 7 changed files with 19 additions and 9 deletions.
diff --git a/.travis.yml b/.travis.yml
@@ -1,3 +1,5 @@
+# TODO: Extend this to do formal as a job and add a job(s) for simulations.
+
 dist: trusty
 sudo: false
 language: generic

diff --git a/impl/warp-v_mips-i_4-stage.tlv b/impl/warp-v_mips-i_4-stage.tlv
@@ -9,5 +9,6 @@ m4+module_def
 \TLV
    m4+warpv()
    m4+warpv_makerchip_cnt10_tb()
+   m4+makerchip_pass_fail()
 \SV
    endmodule
diff --git a/impl/warp-v_risc-v_1-stage.tlv b/impl/warp-v_risc-v_1-stage.tlv
@@ -10,5 +10,6 @@ m4+module_def
 \TLV
    m4+warpv()
    m4+warpv_makerchip_cnt10_tb()
+   m4+makerchip_pass_fail()
 \SV
    endmodule
diff --git a/impl/warp-v_risc-v_4-stage.tlv b/impl/warp-v_risc-v_4-stage.tlv
@@ -9,5 +9,6 @@ m4+module_def
 \TLV
    m4+warpv()
    m4+warpv_makerchip_cnt10_tb()
+   m4+makerchip_pass_fail()
 \SV
    endmodule
diff --git a/impl/warp-v_risc-v_4-stage_retime.tlv b/impl/warp-v_risc-v_4-stage_retime.tlv
@@ -11,5 +11,6 @@ m4+module_def
 \TLV
    m4+warpv()
    m4+warpv_makerchip_cnt10_tb()
+   m4+makerchip_pass_fail()
 \SV
    endmodule
diff --git a/warp-v.tlv b/warp-v.tlv
@@ -2821,6 +2821,16 @@ m4+module_def
    m4+formal()
    '], [''])
 
+// Hookup Makerchip *passed/*failed signals to CPU $passed/$failed.
+// Args:
+//   /_hier: Scope of core(s), e.g. [''] or ['/core[*]'].
+\TLV makerchip_pass_fail(/_hier)
+   |done
+      @0
+         // Assert these to end simulation (before Makerchip cycle limit).
+         *passed = & /top/_hier|fetch/instr>>M4_REG_WR_STAGE$passed;
+         *failed = | /top/_hier|fetch/instr>>M4_REG_WR_STAGE$failed;
+
 \TLV
    /* verilator lint_on WIDTH */  // Let's be strict about bit widths.
    m4_ifelse_block(m4_eval(M4_CORE_CNT > 1), ['1'], ['
@@ -2830,19 +2840,12 @@ m4+module_def
       m4+cpu(/core)
       m4+warpv_makerchip_cnt10_tb()
    //m4+simple_ring(/core, |noc_in, @1, |noc_out, @1, /top<>0$reset, |rg, /trans)
-   |done
-      @0
-         // Assert these to end simulation (before Makerchip cycle limit).
-         *passed = & /top/core[*]|fetch/instr>>M4_REG_WR_STAGE$passed;
-         *failed = | /top/core[*]|fetch/instr>>M4_REG_WR_STAGE$failed;
+   m4+makerchip_pass_fail(core[*])
    '], ['
    // Single Core.
    m4+warpv()
    m4+warpv_makerchip_cnt10_tb()
-   |done
-      @0
-         *passed = /top|fetch/instr>>M4_REG_WR_STAGE$passed;
-         *failed = /top|fetch/instr>>M4_REG_WR_STAGE$failed;
+   m4+makerchip_pass_fail()
    '])
 \SV
    endmodule

diff --git a/warp-v_config.tlv b/warp-v_config.tlv
@@ -38,5 +38,6 @@ m4+module_def
 \TLV
    m4+warpv()
    m4+warpv_makerchip_cnt10_tb()
+   m4+makerchip_pass_fail()
 \SV
    endmodule