Added a file for configuring a WARP-V model.

README.md

@@ -58,7 +58,7 @@ git submodule update
     - An assembler for hard-coded test programs
     - Formal verification in CI (continuous integration testing)
     - Implementation characterized on AWS data-center FPGAs
-  - A small code base (single ~2K-line file (heavily-commented) implements all WARP-V variants, assembler, tests, and formal verification harness)
+  - A small code base (single < 3K-line file (heavily-commented) implements all WARP-V variants, assembler, tests, formal verification harness, and Xilinx implementation)
 
 
 

warp-v.tlv

@@ -240,7 +240,7 @@ m4+definitions(['
    // ISA:
    m4_default(['M4_ISA'], ['RISCV']) // MINI, RISCV, MIPSI, POWER, DUMMY, etc.
    // Select a standard configuration:
-   m4_default(['M4_STANDARD_CONFIG'], ['4-stage'])  // min_area, 1-stage, 4-stage, 6-stage, none (and define individual parameters).
+   m4_default(['M4_STANDARD_CONFIG'], ['4-stage'])  // 1-stage, 4-stage, 6-stage, none (and define individual parameters).
 
    m4_define_hier(['M4_CORE'], 1)  // Cores. If > 1, cores will be connected with a NoC.
    m4_define_hier(['M4_VC'], 2)    // VCs (meaningful if > 1 core).
@@ -310,7 +310,7 @@ m4+definitions(['
             (M4_REG_WR_STAGE, 0),
             (M4_MEM_WR_STAGE, 0),
             (M4_LD_RETURN_ALIGN, 1))
-         m4_define(['M4_BRANCH_PRED'], ['fallthrough'])
+         m4_default(['M4_BRANCH_PRED'], ['fallthrough'])
          m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
       '],
       ['4-stage'], ['
@@ -344,7 +344,7 @@ m4+definitions(['
             (M4_MEM_WR_STAGE, 7),
             (M4_EXTRA_REPLAY_BUBBLE, 1),
             (M4_LD_RETURN_ALIGN, 7))
-         m4_define(['M4_BRANCH_PRED'], ['two_bit'])
+         m4_default(['M4_BRANCH_PRED'], ['two_bit'])
          m4_define_hier(['M4_DATA_MEM_WORDS'], 32)
       ']
    )

warp-v_config.tlv

@@ -0,0 +1,42 @@
+\m4_TLV_version 1d: tl-x.org
+m4+definitions(['
+   // This file can be used to build a coursely-configured implementation of WARP-V within makerchip.com.
+   // This enables exploration of a generated model (as TL-Verilog (without M4 macros) and/or Verilog/SystemVerilog).
+   // Simulation waveforms can be explored.
+   //
+   // High-level settings are described here. For detailed settings, consult the included warp-v.tlv file.
+
+
+   // -----------------------------------------------------------
+   // CONFIGURATION:
+   
+   // ISA. Legal Values: [MINI, RISCV, MIPSI, POWER, DUMMY]
+   m4_define(M4_ISA, RISCV)
+   
+   // Standard configuration. Legal Values: [1-stage, 4-stage, 6-stage, none (and define individual parameters)]
+   m4_define(M4_STANDARD_CONFIG, 4-stage)
+   
+   
+   // OPTIONAL CONFIGURATION:
+   
+   // Branch predictor. Legal Values: [fallthrough, two_bit]
+   // m4_define(M4_BRANCH_PRED, fallthrough)
+   
+   
+   // DETAILED CONFIGURATION:
+   
+   // (See included warp-v.tlv)
+   
+   // -----------------------------------------------------------
+   
+'])
+\SV
+  // Include WARP-V.
+  m4_include_lib(['https://github.com/stevehoover/warp-v/blob/master/warp-v.tlv'])
+
+  m4+module_def
+\TLV
+  m4+warpv()
+  m4+warpv_makerchip_cnt10_tb()
+\SV
+  endmodule