Added links to README.

README.md

@@ -1,4 +1,12 @@
 # warp-v
+
 WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
 It contains a single source file meant to be used within the Makerchip.com IDE.
+<a href="http://www.makerchip.com/sandbox?code_url=https:%2F%2Fraw.githubusercontent.com%2Fstevehoouver%2Fwarp-v%2Fmaster%2Fwarp-v.tlv" target="_blank">Open the latest WARP-V in Makerchip</a>.
+
+There is a Google Drive area for this and other open-source TL-Verilog projects
+<a href="https://drive.google.com/drive/folders/1l9YTvpNZ0km3IlzlPaMvoLdriLw9B8Yk?usp=sharing" target="_blank">here</a>.
 
+Steve Hoover presented early work at DAC 2018:
+  - <a href="http://www.makerchip.com/module/pane/DAC2018_WARP-V_Presentation.pdf" target="_blank">Slides</a>
+  - <a href="http://localhost:8080/module/pane/DAC2018_WARP-V_Poster.pdf" target="_blank">Poster</a>