Still testing travis.

shariethernet · Jun 16, 2021 · 6deba51 · 6deba51
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@@ -10,7 +10,6 @@ WARP-V is an open-source CPU core generator written in TL-Verilog with support f
 WARP-V includes CPU core logic only with no current support for virtual memory, caches, or IOs. RISC-V implementations are formally verified using open-source tools in continuous integration testing.
 
 
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 # Links
 
 ## Explore WARP-V