To kick off CI.

shariethernet · Jun 15, 2021 · 5a10c8c · 5a10c8c
1 parent fed07ce
commit 5a10c8c
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/README.md b/README.md
@@ -10,7 +10,6 @@ WARP-V is an open-source CPU core generator written in TL-Verilog with support f
 WARP-V includes CPU core logic only with no current support for virtual memory, caches, or IOs. RISC-V implementations are formally verified using open-source tools in continuous integration testing.
 
 
-
 # Links
 
 ## Explore WARP-V