Code cleanup using new M4 features.

Eliminated significant blocks of whitespace in post-M4 TLV code.

README.md

@@ -182,3 +182,8 @@ TODO: Add implementation data here.
 ## Retiming Experiments
 
 We utilized the pipeline flexibility of TL-Verilog and WARP-V's pipeline parameterization to experiment with Vivado's ability to retime logic optimally. This showed that it is not necessary to precisely partition the CPU pipeline logic among pipeline stages in order to get good quality results. However, when tools must retime logic, runtime can be significantly impacted. Here is [more detail](doc/retiming.md).
+
+
+# Known Hardware Implementations
+
+  - [Open MPW-7, WARP-V 4-Stage](https://platform.efabless.com/projects/1287)

configurator/src/components/pages/VerilogSettingsForm.js

@@ -32,6 +32,10 @@ export function VerilogSettingsForm({generalSettings, onFormattingChange, onVers
                     <Checkbox value="--bestsv">Optimize SystemVerilog code for readability (versus
                         preserving line association with TL-Verilog source).</Checkbox>
                     <Checkbox value="--noline">Disable `line directive in SV output.</Checkbox>
+                    <Checkbox value="--clkAlways">Use the global/free-running clock for all flip-flops.</Checkbox>
+                    <Checkbox value="--clkEnable">Use enable flip-flops, not clock gating. (Good for FPGAs.)</Checkbox>
+                    <Checkbox value="--clkStageAlways">Apply clock gating/enabling only to the first
+                        of a series of flip-flops. Generally this will be less area, higher power.</Checkbox>
                     <Checkbox value="--fmtDeclSingleton"> Each HDL signal is declared in its own
                         declaration statement
                         with its own type specification.</Checkbox>