It would be nice to benchmark more bytecode sequences with different properties

[mejedi]

The current bytecode sequence has an important property: no instruction appears twice. Hence for each instruction handler the next instruction handler to dispatch to is perfectly predictable. It amplifies the advantage of implementations that replicate instruction dispatch.

In most if not all VMs the next instruction handler to dispatch to is seldom perfectly predictable. It would be nice to benchmark a more complex instruction sequence to get a more realistic estimate.

[shadowofneptune]

Would something like a VM design to run https://en.wikipedia.org/wiki/Rule_110 be a better example?