do simulation and HW build with LLVM on RISCV

Signed-off-by: Axel Heider <axelheider@gmx.de>
seL4 · Jan 11, 2024 · 0ede24e · 0ede24e
1 parent af6b18b
commit 0ede24e
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Showing 2 changed files with 2 additions and 9 deletions.
diff --git a/.github/workflows/sel4test-hw.yml b/.github/workflows/sel4test-hw.yml
@@ -33,11 +33,9 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        march: [armv7a, armv8a, nehalem]
+        # There is no "rv32imac" hardware yet.
+        march: [armv7a, armv8a, nehalem, rv64imac]
         compiler: [gcc, clang]
-        include:
-          - march: rv64imac
-            compiler: gcc
     steps:
     - name: Build
       uses: seL4/ci-actions/sel4test-hw@master

diff --git a/.github/workflows/sel4test-sim.yml b/.github/workflows/sel4test-sim.yml
@@ -21,11 +21,6 @@ jobs:
       matrix:
         march: [armv7a, armv8a, nehalem, rv32imac, rv64imac]
         compiler: [gcc, clang]
-        exclude:
-          - march: rv32imac
-            compiler: clang
-          - march: rv64imac
-            compiler: clang
     steps:
     - uses: seL4/ci-actions/sel4test-sim@master
       with: