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Chisel Book Continous Integration

Switch from SystemVerilog to plain Verilog #220

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Switch from SystemVerilog to plain Verilog

Switch from SystemVerilog to plain Verilog #220

Workflow file for this run

.github/workflows/test.yml at 93a8a33
name: Chisel Book Continous Integration
on:
push:
branches: [ master ]
pull_request:
branches: [ master ]
jobs:
run-tests:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: Set up JDK 11
uses: actions/setup-java@v2
with:
java-version: '11'
distribution: 'temurin'
- name: Setup Verilator
# should include texlive-full for Latex test
run: sudo apt-get install verilator
- name: Setup z3
run: sudo apt-get install z3
- name: Run tests
run: sbt test
# should run make for the test including Latex
# - name: Build book
# run: |
# make gencode
# make fig
# make book