@@ -103,7 +103,7 @@ regular_func div_s32s32
103103regular_func divmod_s32s32
104104#if !PICO_DIVIDER_DISABLE_INTERRUPTS
105105 // to support IRQ usage ( or context switch) we must save/restore divider state around call if state is dirty
106- ldr r2 , =( SIO_BASE)
106+ ldr r2 , =SIO_BASE
107107 ldr r3 , [ r2 , #SIO_DIV_CSR_OFFSET ]
108108 lsrs r3 , #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
109109 bcs divmod_s32s32_savestate
@@ -114,7 +114,7 @@ regular_func divmod_s32s32_unsafe
114114// are the hardware_divider functions th at can be used instead anyway
115115regular_func divmod_s32s32_unsafe
116116 // to avoid worrying about IRQs ( or context switches) , simply disable interrupts around call
117- ldr r2 , =( SIO_BASE)
117+ ldr r2 , =SIO_BASE
118118 mrs r3 , PRIMASK
119119 cpsid i
120120#endif / * !PICO_DIVIDER_DISABLE_INTERRUPTS * /
@@ -167,7 +167,7 @@ wrapper_func __aeabi_uidiv
167167wrapper_func __aeabi_uidivmod
168168#if !PICO_DIVIDER_DISABLE_INTERRUPTS
169169 // to support IRQ usage ( or context switch) we must save/restore divider state around call if state is dirty
170- ldr r2 , =( SIO_BASE)
170+ ldr r2 , =SIO_BASE
171171 ldr r3 , [ r2 , #SIO_DIV_CSR_OFFSET ]
172172 lsrs r3 , #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
173173 bcs divmod_u32u32_savestate
@@ -178,7 +178,7 @@ regular_func divmod_u32u32_unsafe
178178// are the hardware_divider functions th at can be used instead anyway
179179regular_func divmod_u32u32_unsafe
180180 // to avoid worrying about IRQs ( or context switches) , simply disable interrupts around call
181- ldr r2 , =( SIO_BASE)
181+ ldr r2 , =SIO_BASE
182182 mrs r3 , PRIMASK
183183 cpsid i
184184#endif / * !PICO_DIVIDER_DISABLE_INTERRUPTS * /
@@ -227,7 +227,7 @@ regular_func divmod_s64s64
227227#if !PICO_DIVIDER_DISABLE_INTERRUPTS
228228 // to support IRQ usage ( or context switch) we must save/restore divider state around call if state is dirty
229229 mov ip , r2
230- ldr r2 , =( SIO_BASE)
230+ ldr r2 , =SIO_BASE
231231 ldr r2 , [ r2 , #SIO_DIV_CSR_OFFSET ]
232232 lsrs r2 , #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
233233 mov r2 , ip
@@ -255,7 +255,7 @@ regular_func divmod_u64u64
255255#if !PICO_DIVIDER_DISABLE_INTERRUPTS
256256 // to support IRQ usage ( or context switch) we must save/restore divider state around call if state is dirty
257257 mov ip , r2
258- ldr r2 , =( SIO_BASE)
258+ ldr r2 , =SIO_BASE
259259 ldr r2 , [ r2 , #SIO_DIV_CSR_OFFSET ]
260260 lsrs r2 , #SIO_DIV_CSR_DIRTY_SHIFT_FOR_CARRY
261261 mov r2 , ip
@@ -278,7 +278,7 @@ regular_func divmod_u64u64_savestate
278278
279279.macro dneg lo , hi
280280 mvns \hi , \hi
281- rsbs \lo , # 0
281+ negs \lo , \lo
282282 bne l\@_1
283283 adds \hi , # 1
284284l\@_1:
@@ -352,7 +352,7 @@ regular_func divmod_u64u64_unsafe
352352 cmp r2 , # 0
353353 beq 2f @ x== 0 ?
354354 mov r12 , r7
355- ldr r7 , =# SIO_BASE
355+ ldr r7 , =SIO_BASE
356356 str r0 ,[ r7 , #SIO_DIV_UDIVIDEND_OFFSET ]
357357 str r2 ,[ r7 , #SIO_DIV_UDIVISOR_OFFSET ]
358358 movs r1 , # 0
@@ -367,7 +367,7 @@ regular_func divmod_u64u64_unsafe
367367 cmp r0 , # 0 @ y== 0 ?
368368 beq 3f @ then pass 0 to __aeabi_ldiv0
369369udiv0:
370- ldr r0 , =# 0xffffffff
370+ ldr r0 , = 0xffffffff
371371 movs r1 , r0 @ pass 2 ^ 64 - 1 to __aeabi_ldiv0
3723723 :
373373 push { r14 }
402402 cmp r2 , # 0
403403 beq udiv0 @ x== 0 ? exit as with y!= 0 case above
404404 push {r7}
405- ldr r7 , =# SIO_BASE
405+ ldr r7 , =SIO_BASE
406406 str r1 ,[ r7 , #SIO_DIV_UDIVIDEND_OFFSET ]
407407 str r2 ,[ r7 , #SIO_DIV_UDIVISOR_OFFSET ]
408408 wait_div 4
@@ -464,9 +464,9 @@ y64_x32:
464464 lsrs r4 , r2 , # 15
465465 adds r4 , # 1 @ x1=(x0>> 15 ) + 1 ; 2^16<x1<=2^17
466466
467- ldr r7 , =# SIO_BASE
467+ ldr r7 , =SIO_BASE
468468 str r4 ,[ r7 , #SIO_DIV_UDIVISOR_OFFSET ]
469- ldr r4 , =# 0xffffffff
469+ ldr r4 , = 0xffffffff
470470 str r4 ,[ r7 , #SIO_DIV_UDIVIDEND_OFFSET ]
471471 lsrs r6 , r1 , # 16
472472 uxth r3 , r2 @ x0l
@@ -687,9 +687,9 @@ y64_x48:
687687 adcs r4 , r4
688688 adds r4 , # 1 @ x1=(ui32)(x0>> 31 ) + 1 ; // 2^16<x1<=2^17
689689
690- ldr r7 , =# SIO_BASE
690+ ldr r7 , =SIO_BASE
691691 str r4 ,[ r7 , #SIO_DIV_UDIVISOR_OFFSET ]
692- ldr r4 , =# 0xffffffff
692+ ldr r4 , = 0xffffffff
693693 str r4 ,[ r7 , #SIO_DIV_UDIVIDEND_OFFSET ]
694694 lsrs r6 , r1 , # 16
695695 wait_div 1
@@ -821,7 +821,7 @@ y64_x64:
821821 adds r5 , r3 , # 1
822822 beq 1f
823823
824- ldr r7 , =# SIO_BASE
824+ ldr r7 , =SIO_BASE
825825 str r5 ,[ r7 , #SIO_DIV_UDIVISOR_OFFSET ]
826826 str r1 ,[ r7 , #SIO_DIV_UDIVIDEND_OFFSET ]
827827 wait_div 0
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