Update XLS[cc] examples.

--reset_data_path=true gives unsupported error in single function block conversion.
PiperOrigin-RevId: 711459111

docs_src/tutorials/xlscc_memory.md

@@ -92,19 +92,19 @@ rewrites {
   }
   from_channels_logical_to_physical: {
     key: "abstract_read_req"
-    value: "store__read_request"
+    value: "store_read_request"
   }
   from_channels_logical_to_physical: {
     key: "abstract_read_resp"
-    value: "store__read_response"
+    value: "store_read_response"
   }
   from_channels_logical_to_physical: {
     key: "abstract_write_req"
-    value: "store__write_request"
+    value: "store_write_request"
   }
   from_channels_logical_to_physical: {
     key: "write_completion"
-    value: "store__write_response"
+    value: "store_write_response"
   }
   to_name_prefix: "store_"
 }
@@ -136,16 +136,12 @@ $ ./bazel-bin/xls/tools/codegen_main test_memory.opt.ir \
   --pipeline_stages=2  \
   --flop_inputs=false \
   --flop_outputs=false \
-  --io_constraints=store__read_req:send:store__read_resp:recv:1:1,store__write_req:send:store__write_completion:recv:1:1 \
   --ram_configurations=ram:1R1W:store__read_req:store__read_resp:store__write_req:store__write_completion
 ```
 
 Below is a quick summary of the options.
 
-1.  `--io_constraints=store__read_req:send:store__read_resp:recv:1:1...` This
-    option ensures that requests to the memory are written exactly 1 cycle
-    before responses are read.
-2.  `--ram_configurations=ram:1R1W:store__read_req...` This option informs
+1.  `--ram_configurations=ram:1R1W:store__read_req...` This option informs
     codegen of the necessary information about the memory to generate the top
     level ports in the correct style. "ram" is the name prefix the ports will
     use.

docs_src/tutorials/xlscc_overview.md

@@ -131,10 +131,9 @@ $ ./bazel-bin/xls/tools/codegen_main test_unroll.opt.ir \
   --delay_model="asap7" \
   --output_verilog_path=test_unroll.v \
   --module_name=xls_test_unroll \
-  --entry=test_unroll \
+  --top=test_unroll \
   --reset=rst \
-  --reset_active_low=false \
-  --reset_asynchronous=false \
+  --reset_data_path=false \
   --pipeline_stages=5 \
   --flop_inputs=true \
   --flop_outputs=true

docs_src/tutorials/xlscc_pipelined_loops.md

@@ -25,7 +25,7 @@ public:
     #pragma hls_top
     void Run() {
     int sum = 0;
-        #pragma hls_pipeline_unroll yes
+        #pragma hls_pipeline_init_interval 1
         for(int i=0;i<4;++i) {
             sum += in.read();
         }
@@ -42,11 +42,9 @@ Use a combination of `xlscc` and `opt_main` to generate optimized XLS IR.
 $ ./bazel-bin/xls/contrib/xlscc/xlscc test_loop.cc \
   --block_from_class TestBlock --block_pb block.pb \
   > test_loop.ir
-$ ./bazel-bin/xls/tools/opt_main test_loop.ir --inline_procs > test_loop.opt.ir
+$ ./bazel-bin/xls/tools/opt_main test_loop.ir > test_loop.opt.ir
 ```
 
-The `--inline_procs` option is necessary to make pipelined loops synthesizable.
-
 ## Examine the optimized IR
 
 `test_loop.opt.ir` should look like this, containing only one proc:

xls/contrib/xlscc/README.md

@@ -40,7 +40,7 @@ To generate some verilog:
 
 ```console
 echo "#pragma hls_top
-int add3(int input) { return input+3; }" > test.cc
+int add3(int x) { return x+3; }" > test.cc
 
 bazel build -c opt //xls/contrib/xlscc:xlscc //xls/tools:opt_main //xls/tools:codegen_main
 bazel-bin/xls/contrib/xlscc/xlscc test.cc > test.ir