Processor Spec Un-Availability Enhancements #291
Description
A problem recently arose in the construction of experiment designs where it was decided that it was desirable to restrict the form of the parallel layers allowed in the construction of DRB experiments. In particular, DRB by default inherits the allowable layers that is samples from from the availability attribute (or geometry) of its processor spec. I wanted to impose a restriction on which gates were allowed in parallel with each other, but couldn't identify any way to specify this naturally with the existing API. Some way of adding either exceptions to the availability or otherwise extending the expressiveness of the API to handle that case would be a valuable addition to the processor spec.