Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Wrapper for Rocket-Chip on FPGAs

Gem5 with PCI Express integrated.

A set of configurations to model Arm's N1 cores.

This repo contains instructions, benchmarks, and files for running user space networking in gem5 simulator.

Random instruction generator for RISC-V processor verification

Direct Memory Access (DMA) Attack Software

RISC-V IOMMU Demo (Linux & Bao)

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

RISC-V IOMMU Specification

This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.

Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)

RISC-V Assembly Programmer's Manual

Convolutional Neural Network in C

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

RTL, Cmodel, and testbench for NVDLA

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

RISC-V Linux Port