Embedded-Deep-Neural-Network-Processing

本研究在PYNQ板上對PS端進行Verilog編寫，並完成CNN、Maxpooling、Fully Connected在 Vivado中的設計，其中大數乘法採用位移乘法運算，以確保所設計的硬體模塊能夠正確且有效地被 PYNQ板上的可程式邏輯（PL）部分使用。

PYNQ FPGA-based CNN Accelerator Design

• Implemented CNN layers (Convolution, Maxpooling, Fully Connected) in Verilog using Vivado.

• Designed a shift-and-add multiplier for efficient hardware multiplication without DSP blocks.

• Integrated PS–PL communication on PYNQ board to validate functionality and performance.

• Verified functionality via testbench simulation and on-board testing.

---

第八組海報