first commit

LICENSE

@@ -0,0 +1 @@
+All the files of this project are under GNU GPL

Makefile

@@ -0,0 +1,50 @@
+# OS Main Makefile
+
+OUTPUT		:= os.img
+
+Q := @
+MAKEFLAGS	+= --no-print-directory
+MAKE		:= make
+TARGETS		:= libc kernel
+
+# Compiler settings
+PREFIX		:= i386-elf-
+GDB			:= $(PREFIX)gdb
+
+
+rebuild:
+	@echo "--> Rebuilding OS"
+	@for dir in $(TARGETS); do $(MAKE) -C $$dir rebuild; done
+	@echo "--> Generating $(OUTPUT)"
+	@cp kernel/kernel.elf isofs/boot/kernel.elf
+	@genisoimage -R -b boot/grub/stage2_eltorito -no-emul-boot -boot-load-size 4 -boot-info-table -quiet -o $(OUTPUT) isofs
+	@echo "--> Build finished"
+
+default:
+	@echo "--> Building OS"
+	@for dir in $(TARGETS); do $(MAKE) -C $$dir default; done
+	@echo "--> Generating $(OUTPUT)"
+	@cp kernel/kernel.elf isofs/boot/kernel.elf
+	@genisoimage -R -b boot/grub/stage2_eltorito -no-emul-boot -boot-load-size 4 -boot-info-table -quiet -o $(OUTPUT) isofs
+	@echo "--> Build finished"
+
+clean:
+	@echo "--> Cleaning OS"
+	@for dir in $(TARGETS); do $(MAKE) -C $$dir clean; done
+	@rm $(OUTPUT)
+	@echo "--> Build finished"
+
+debug:
+	@echo "--> Building OS (debug)"
+	@for dir in $(TARGETS); do $(MAKE) -C $$dir debug; done
+	@echo "--> Generating $(OUTPUT)"
+	@cp kernel/kernel.elf isofs/boot/kernel.elf
+	@genisoimage -R -b boot/grub/stage2_eltorito -no-emul-boot -boot-load-size 4 -boot-info-table -quiet -o $(OUTPUT) isofs
+	@echo "--> Build finished"
+	@echo "--> Starting emulator and debugger"
+	@qemu-system-i386 -s -cdrom $(OUTPUT) -d guest_errors,int &
+	@$(GDB) -ex "target remote localhost:1234" -ex "symbol-file kernel/kernel.elf"
+
+run: rebuild
+	@echo "--> Starting emulator"
+	@qemu-system-i386 -cdrom $(OUTPUT) -m 512M

README.md

@@ -0,0 +1,7 @@
+# OS  
+## I did not find a better name for it yet.  
+
+It's pretty bad for now but hopefully it will be fixed sometime.  
+heap is currently randomly causing page faults. there must be something weird with it.  
+
+(some info was taken from the osdev wiki, the little book about kernel development and jamesm's tutorials)  

isofs/boot/grub/menu.lst

@@ -0,0 +1,6 @@
+default 0
+#timeout 1
+
+title OS
+kernel /boot/kernel.elf
+module /boot/initrd.img

kernel/Makefile

@@ -0,0 +1,70 @@
+# OS Makefile
+
+Q := @
+MAKEFLAGS += --no-print-directory
+
+TARGET		:= kernel.elf
+
+# Autogenerate a list of source files
+SOURCEDIR	:= .
+C_SOURCES	:= $(shell find $(SOURCEDIR) -name '*.c')
+A_SOURCES	:= $(shell find $(SOURCEDIR) -name '*.s')
+C_HEADERS	:= $(shell find $(SOURCEDIR) -name '*.h')
+
+# Generate object files from source files
+BUILD_DIR	:= build
+C_OBJ		:= $(C_SOURCES:.c=.o)
+A_OBJ		:= $(A_SOURCES:.s=.o)
+
+# Compiler settings
+PREFIX		:= i386-elf-
+CC			:= $(PREFIX)gcc
+GDB			:= $(PREFIX)gdb
+LD			:= $(PREFIX)ld
+AS			:= nasm
+
+# Include kernel and libc headers
+INCLUDES	:=	-I include \
+				-I ../libc/include
+
+# Build flags
+CFLAGS		:=	-g -m32 \
+				-ffreestanding -fstack-protector -fno-exceptions \
+				-Wall -Wextra -Wno-unused ${INCLUDES}
+
+# Rebuild by default
+rebuild: clean default
+
+# Debug
+debug:
+	@echo "-> Building Kernel (debug)"
+	@mkdir -p $(BUILD_DIR)
+	@$(MAKE) $(TARGET_DBG)
+
+# Create build directory
+default:
+	@echo "-> Building Kernel"
+	@mkdir -p $(BUILD_DIR)
+	@$(MAKE) $(TARGET)
+
+# Build target
+$(TARGET): $(A_OBJ) $(C_OBJ)
+	@echo "LD $@"
+	@$(LD) -T link.ld -o $@ $(addprefix $(BUILD_DIR)/, $(notdir $^)) ../libc/libk.a
+
+# Build target (debug) - no changes for now
+$(TARGET_DBG): $(TARGET)
+
+# Generic rules for wildcards
+# To make an object, always compile from its .c
+%.o: %.c $(C_HEADERS)
+	@echo "CC $<"
+	@$(CC) $(CFLAGS) -c $< -o $(BUILD_DIR)/$(notdir $@)
+
+%.o: %.s
+	@echo "AS $<"
+	@$(AS) $< -f elf -o $(BUILD_DIR)/$(notdir $@)
+
+clean:
+	@echo "-> Cleaning Kernel"
+	@rm -rf $(TARGET) $(BUILD_DIR)

kernel/arch/x86/fpu.s

@@ -0,0 +1,22 @@
+; Doesn't work right now. not really needed until starting the graphics work....
+; global fpu_init
+; 
+; fpu_init:
+; 	; Search for an FPU
+; 	mov edx, cr0							; Start probe, get cr0
+; 	and edx, (-1) - (cr0_ts + cr0_em)		; clear TS and EM to force fpu access
+; 	mov cr0, edx							; store control word
+; 	fninit									; load defaults to FPU
+; 	fnstsw [testword]						; store status word
+; 	cmp word [testword], 0					; compare the written status with the expected FPU state
+; 	jne nofpu								; jump if the FPU hasn't written anything (i.e. it's not there)
+; 	jmp hasfpu
+; 	 
+; testword dw 0xAABB            		        ; store garbage to be able to detect a change
+; 
+; hasfpu:
+; 	
+; 	ret
+; 
+; nofpu:
+; 	ret

kernel/arch/x86/gdt.s

@@ -0,0 +1,63 @@
+; gdt.s
+;
+; Sets up an unprotected GDT (overlaps code and data) covering the full memory address
+; Protection could easily be setup but it's not really needed when already using paging
+;
+; Based on os-dev.pdf
+; Adapted to work on pretected mode
+;
+
+; GDT null segment
+gdt_start:
+    dd 0x0 ; 4 byte
+    dd 0x0 ; 4 byte
+
+; GDT code segment
+gdt_code: 
+    dw 0xffff    ; segment length, bits 0-15
+    dw 0x0       ; segment base, bits 0-15
+    db 0x0       ; segment base, bits 16-23
+    db 10011010b ; flags (8 bits)
+    db 11001111b ; flags (4 bits) + segment length, bits 16-19
+    db 0x0       ; segment base, bits 24-31
+
+; GDT data segment
+gdt_data:
+    dw 0xffff
+    dw 0x0
+    db 0x0
+    db 10010010b
+    db 11001111b
+    db 0x0
+
+gdt_end:
+
+; GDT descriptor
+gdt_descriptor:
+    dw gdt_end - gdt_start - 1	; size		(16 bit)
+    dd gdt_start				; address	(32 bit)
+
+CODE_SEG equ gdt_code - gdt_start
+DATA_SEG equ gdt_data - gdt_start
+
+; Load the GDT
+global gdt_init
+gdt_init:
+	; Load the gdt
+	lgdt [gdt_descriptor]
+
+	; Far jump to "enable" the GDT
+	jmp CODE_SEG:gdt_flush
+
+; Update the segment registers
+gdt_flush:
+	; Update data segment
+	mov ax, DATA_SEG
+	mov ds, ax
+	mov ss, ax
+	mov es, ax
+	mov fs, ax
+	mov gs, ax
+
+	; Return
+	ret

kernel/arch/x86/idt.c

@@ -0,0 +1,19 @@
+#include <arch/x86/idt.h>
+#include <stdint.h>
+
+void set_idt_gate(int n, u32 handler)
+{
+    idt[n].low_offset = (u16)((handler) & 0xFFFF);
+    idt[n].sel = KERNEL_CS;
+    idt[n].zero = 0;
+    idt[n].flags = 0x8E; 
+    idt[n].high_offset = (u16)(((handler) >> 16) & 0xFFFF);
+}
+
+void set_idt()
+{
+    idt_reg.base = (u32) &idt;
+    idt_reg.limit = IDT_ENTRIES * sizeof(idt_gate_t) - 1;
+    // Don't make the mistake of loading &idt -- always load &idt_reg
+    asm volatile("lidtl (%0)" : : "r" (&idt_reg));
+}

kernel/arch/x86/interrupt.s

@@ -0,0 +1,145 @@
+; Defined in isr.c
+extern isr_handler
+extern irq_handler
+
+; Define some nasm macros to avoid copypasting functions 47 times (who wants to do that?)
+
+%macro ISR 1		; ISR [isr number]
+	global isr%1
+	isr%1:
+		push byte 0 ; Replace error code with 0
+		push byte %1
+		jmp isr_common_stub
+%endmacro
+
+%macro ISR_ERR 1	; ISR_ERR [isr number]
+	global isr%1
+	isr%1:
+		push byte %1
+		jmp isr_common_stub
+%endmacro
+
+%macro IRQ 2		; IRQ [isr number], [irq number]
+	global irq%2
+	irq%2:
+		push byte %2
+		push byte %1
+		jmp irq_common_stub
+%endmacro
+
+; ISRs
+ISR 0		; Divide By Zero Exception
+ISR 1		; Debug Exception
+ISR 2		; Non Maskable Interrupt Exception
+ISR 3		; Int 3 Exception
+ISR 4		; INTO Exception
+ISR 5		; Out of Bounds Exception
+ISR 6		; Invalid Opcode Exception
+ISR 7		; Coprocessor Not Available Exception
+ISR_ERR 8	; Double Fault Exception (With Error Code!)
+ISR 9		; Coprocessor Segment Overrun Exception
+ISR_ERR 10	; Bad TSS Exception (With Error Code!)
+ISR_ERR 11	; Segment Not Present Exception (With Error Code!)
+ISR_ERR 12	; Stack Fault Exception (With Error Code!)
+ISR_ERR 13	; General Protection Fault Exception (With Error Code!)
+ISR_ERR 14	; Page Fault Exception (With Error Code!)
+ISR 15		; Reserved Exception
+ISR 16		; Floating Point Exception
+ISR 17		; Alignment Check Exception
+ISR 18		; Machine Check Exception
+ISR 19		; Reserved
+ISR 20		; Reserved
+ISR 21		; Reserved
+ISR 22		; Reserved
+ISR 23		; Reserved
+ISR 24		; Reserved
+ISR 25		; Reserved
+ISR 26		; Reserved
+ISR 27		; Reserved
+ISR 28		; Reserved
+ISR 29		; Reserved
+ISR 30		; Reserved
+ISR 31		; Reserved
+
+; IRQs
+IRQ 32, 0
+IRQ 33, 1
+IRQ 34, 2
+IRQ 35, 3
+IRQ 36, 4
+IRQ 37, 5
+IRQ 38, 6
+IRQ 39, 7
+IRQ 40, 8
+IRQ 41, 9
+IRQ 42, 10
+IRQ 43, 11
+IRQ 44, 12
+IRQ 45, 13
+IRQ 46, 14
+IRQ 47, 15
+
+
+; Common ISR code
+isr_common_stub:
+    ; Save CPU state
+	pusha		; Pushes edi,esi,ebp,esp,ebx,edx,ecx,eax
+	mov ax, ds	; Lower 16-bits of eax = ds
+
+	; Save the current data segment
+	push eax
+
+	; Switch to kernel data segment
+	mov ax, 0x10
+	mov ds, ax
+	mov es, ax
+	mov fs, ax
+	mov gs, ax
+
+	; Call C handler
+	push esp	; registers_t *r
+    cld			; C code following the sysV ABI requires DF to be clear on function entry
+	call isr_handler
+
+    ; Restore CPU state
+	pop eax 
+    pop eax
+	mov ds, ax
+	mov es, ax
+	mov fs, ax
+	mov gs, ax
+	popa
+	add esp, 8	; Cleans up the pushed error code and pushed ISR number
+	iret		; pops 5 things at once: CS, EIP, EFLAGS, SS, and ESP
+
+; Common IRQ code. Identical to ISR code except for the 'call' and the 'pop ebx'
+irq_common_stub:
+	; Save CPU state
+    pusha 
+    mov ax, ds
+
+	; Save current data segment
+    push eax
+
+	; Switch to kernel data segment
+    mov ax, 0x10
+    mov ds, ax
+    mov es, ax
+    mov fs, ax
+    mov gs, ax
+
+	; Call C handler
+    push esp			; registers_t *r
+    cld
+    call irq_handler	; Common IRQ handler
+
+	; Restore CPU state
+    pop ebx  ; Different than the ISR code
+    pop ebx
+    mov ds, bx
+    mov es, bx
+    mov fs, bx
+    mov gs, bx
+    popa
+    add esp, 8
+    iret