Adding the x86 part of behavioural testing for std::arch intrinsics

ci/run-docker.sh

@@ -37,6 +37,7 @@ run() {
       --env NORUN \
       --env RUSTFLAGS \
       --env CARGO_UNSTABLE_BUILD_STD \
+      --env RUST_STD_DETECT_UNSTABLE \
       --volume "${HOME}/.cargo":/cargo \
       --volume "$(rustc --print sysroot)":/rust:ro \
       --volume "$(pwd)":/checkout:ro \

ci/run.sh

@@ -10,7 +10,7 @@ set -ex
 #export RUST_TEST_NOCAPTURE=1
 #export RUST_TEST_THREADS=1
 
-export RUSTFLAGS="${RUSTFLAGS} -D warnings -Z merge-functions=disabled "
+export RUSTFLAGS="${RUSTFLAGS} -D warnings -Z merge-functions=disabled -Z verify-llvm-ir"
 export HOST_RUSTFLAGS="${RUSTFLAGS}"
 export PROFILE="${PROFILE:="--profile=release"}"
 

crates/core_arch/src/aarch64/neon/mod.rs

@@ -13,7 +13,7 @@ pub use self::generated::*;
 use crate::{
     core_arch::{arm_shared::*, simd::*},
     hint::unreachable_unchecked,
-    intrinsics::simd::*,
+    intrinsics::{simd::*, *},
     mem::transmute,
 };
 #[cfg(test)]

crates/core_arch/src/arm_shared/neon/mod.rs

@@ -62,8 +62,6 @@ types! {
     pub struct int16x4_t(4 x pub(crate) i16);
     /// Arm-specific 64-bit wide vector of four packed `u16`.
     pub struct uint16x4_t(4 x pub(crate) u16);
-    //  Arm-specific 64-bit wide vector of four packed `f16`.
-    pub struct float16x4_t(4 x pub(crate) f16);
     /// Arm-specific 64-bit wide vector of four packed `p16`.
     pub struct poly16x4_t(4 x pub(crate) p16);
     /// Arm-specific 64-bit wide vector of two packed `i32`.
@@ -89,8 +87,6 @@ types! {
     pub struct int16x8_t(8 x pub(crate) i16);
     /// Arm-specific 128-bit wide vector of eight packed `u16`.
     pub struct uint16x8_t(8 x pub(crate) u16);
-    //  Arm-specific 128-bit wide vector of eight packed `f16`.
-    pub struct float16x8_t(8 x pub(crate) f16);
     /// Arm-specific 128-bit wide vector of eight packed `p16`.
     pub struct poly16x8_t(8 x pub(crate) p16);
     /// Arm-specific 128-bit wide vector of four packed `i32`.
@@ -107,6 +103,15 @@ types! {
     pub struct poly64x2_t(2 x pub(crate) p64);
 }
 
+types! {
+    #![unstable(feature = "stdarch_neon_f16", issue = "136306")]
+
+    /// Arm-specific 64-bit wide vector of four packed `f16`.
+    pub struct float16x4_t(4 x pub(crate) f16);
+    /// Arm-specific 128-bit wide vector of eight packed `f16`.
+    pub struct float16x8_t(8 x pub(crate) f16);
+}
+
 /// Arm-specific type containing two `int8x8_t` vectors.
 #[repr(C)]
 #[derive(Copy, Clone, Debug)]

crates/core_arch/src/loongarch64/mod.rs

@@ -329,16 +329,18 @@ pub unsafe fn asrtgt(a: i64, b: i64) {
 
 /// Loads the page table directory entry
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub unsafe fn lddir(a: i64, b: i64) -> i64 {
-    __lddir(a, b)
+pub unsafe fn lddir<const B: i64>(a: i64) -> i64 {
+    __lddir(a, B)
 }
 
 /// Loads the page table entry
 #[inline]
+#[rustc_legacy_const_generics(1)]
 #[unstable(feature = "stdarch_loongarch", issue = "117427")]
-pub unsafe fn ldpte(a: i64, b: i64) {
-    __ldpte(a, b)
+pub unsafe fn ldpte<const B: i64>(a: i64) {
+    __ldpte(a, B)
 }
 
 /// Calculate the approximate single-precision result of 1.0 divided

crates/core_arch/src/powerpc/altivec.rs

@@ -338,26 +338,26 @@ unsafe extern "C" {
     #[link_name = "llvm.ppc.altivec.vlogefp"]
     fn vlogefp(a: vector_float) -> vector_float;
 
-    #[link_name = "llvm.ppc.altivec.sll"]
+    #[link_name = "llvm.ppc.altivec.vsl"]
     fn vsl(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
-    #[link_name = "llvm.ppc.altivec.slo"]
+    #[link_name = "llvm.ppc.altivec.vslo"]
     fn vslo(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
 
-    #[link_name = "llvm.ppc.altivec.srab"]
+    #[link_name = "llvm.ppc.altivec.vsrab"]
     fn vsrab(a: vector_signed_char, b: vector_unsigned_char) -> vector_signed_char;
-    #[link_name = "llvm.ppc.altivec.srah"]
+    #[link_name = "llvm.ppc.altivec.vsrah"]
     fn vsrah(a: vector_signed_short, b: vector_unsigned_short) -> vector_signed_short;
-    #[link_name = "llvm.ppc.altivec.sraw"]
+    #[link_name = "llvm.ppc.altivec.vsraw"]
     fn vsraw(a: vector_signed_int, b: vector_unsigned_int) -> vector_signed_int;
 
-    #[link_name = "llvm.ppc.altivec.srl"]
+    #[link_name = "llvm.ppc.altivec.vsr"]
     fn vsr(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
-    #[link_name = "llvm.ppc.altivec.sro"]
+    #[link_name = "llvm.ppc.altivec.vsro"]
     fn vsro(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
 
-    #[link_name = "llvm.ppc.altivec.slv"]
+    #[link_name = "llvm.ppc.altivec.vslv"]
     fn vslv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
-    #[link_name = "llvm.ppc.altivec.srv"]
+    #[link_name = "llvm.ppc.altivec.vsrv"]
     fn vsrv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
 
     #[link_name = "llvm.fshl.v16i8"]

crates/core_arch/src/s390x/vector.rs

@@ -174,9 +174,9 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.s390.vpklsfs"] fn vpklsfs(a: vector_unsigned_int, b: vector_unsigned_int) -> PackedTuple<vector_unsigned_short, i32>;
     #[link_name = "llvm.s390.vpklsgs"] fn vpklsgs(a: vector_unsigned_long_long, b: vector_unsigned_long_long) -> PackedTuple<vector_unsigned_int, i32>;
 
-    #[link_name = "llvm.s390.vuplbw"] fn vuplbw (a: vector_signed_char) -> vector_signed_short;
+    #[link_name = "llvm.s390.vuplb"] fn vuplb (a: vector_signed_char) -> vector_signed_short;
     #[link_name = "llvm.s390.vuplhw"] fn vuplhw (a: vector_signed_short) -> vector_signed_int;
-    #[link_name = "llvm.s390.vuplfw"] fn vuplfw (a: vector_signed_int) -> vector_signed_long_long;
+    #[link_name = "llvm.s390.vuplf"] fn vuplf (a: vector_signed_int) -> vector_signed_long_long;
     #[link_name = "llvm.s390.vupllb"] fn vupllb (a: vector_unsigned_char) -> vector_unsigned_short;
     #[link_name = "llvm.s390.vupllh"] fn vupllh (a: vector_unsigned_short) -> vector_unsigned_int;
     #[link_name = "llvm.s390.vupllf"] fn vupllf (a: vector_unsigned_int) -> vector_unsigned_long_long;
@@ -2581,9 +2581,9 @@ mod sealed {
     // FIXME(llvm): a shuffle + simd_as does not currently optimize into a single instruction like
     // unpachk above. Tracked in https://github.com/llvm/llvm-project/issues/129576.
 
-    impl_vec_trait! {[VectorUnpackl vec_unpackl] vuplbw (vector_signed_char) -> vector_signed_short}
+    impl_vec_trait! {[VectorUnpackl vec_unpackl] vuplb (vector_signed_char) -> vector_signed_short}
     impl_vec_trait! {[VectorUnpackl vec_unpackl] vuplhw (vector_signed_short) -> vector_signed_int}
-    impl_vec_trait! {[VectorUnpackl vec_unpackl] vuplfw (vector_signed_int) -> vector_signed_long_long}
+    impl_vec_trait! {[VectorUnpackl vec_unpackl] vuplf (vector_signed_int) -> vector_signed_long_long}
 
     impl_vec_trait! {[VectorUnpackl vec_unpackl] vupllb (vector_unsigned_char) -> vector_unsigned_short}
     impl_vec_trait! {[VectorUnpackl vec_unpackl] vupllh (vector_unsigned_short) -> vector_unsigned_int}
@@ -3011,9 +3011,9 @@ mod sealed {
                     #[inline]
                     #[target_feature(enable = "vector")]
                     unsafe fn vec_sel(self, b: Self, c: t_u!($ty)) -> Self {
-                        let b = simd_and(b, transmute(c));
-                        let a = simd_and(self, simd_xor(transmute(c), transmute(vector_signed_char([!0; 16]))));
-                        simd_or(a, b)
+                        let b = simd_and(transmute(b), c);
+                        let a = simd_and(transmute(self), simd_xor(c, transmute(vector_signed_char([!0; 16]))));
+                        transmute(simd_or(a, b))
                     }
                 }
 
@@ -3198,14 +3198,14 @@ mod sealed {
                 #[unstable(feature = "stdarch_s390x", issue = "135681")]
                 impl VectorSearchString for $ty {
                     #[inline]
-                    #[target_feature(enable = "vector")]
+                    #[target_feature(enable = "vector-enhancements-2")]
                     unsafe fn vec_search_string_cc(self, b: Self, c: vector_unsigned_char) -> (vector_unsigned_char, i32) {
                         let PackedTuple { x,y } = $intr_s(transmute(self), transmute(b), c);
                         (x, y)
                     }
 
                     #[inline]
-                    #[target_feature(enable = "vector")]
+                    #[target_feature(enable = "vector-enhancements-2")]
                     unsafe fn vec_search_string_until_zero_cc(self, b: Self, c: vector_unsigned_char) -> (vector_unsigned_char, i32) {
                         let PackedTuple { x,y } = $intr_sz(transmute(self), transmute(b), c);
                         (x, y)

crates/core_arch/src/wasm32/simd128.rs

@@ -110,9 +110,9 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.wasm.avgr.unsigned.v8i16"]
     fn llvm_avgr_u_i16x8(a: simd::i16x8, b: simd::i16x8) -> simd::i16x8;
 
-    #[link_name = "llvm.wasm.extadd.pairwise.signed.v16i8"]
+    #[link_name = "llvm.wasm.extadd.pairwise.signed.v4i32"]
     fn llvm_i32x4_extadd_pairwise_i16x8_s(x: simd::i16x8) -> simd::i32x4;
-    #[link_name = "llvm.wasm.extadd.pairwise.unsigned.v16i8"]
+    #[link_name = "llvm.wasm.extadd.pairwise.unsigned.v4i32"]
     fn llvm_i32x4_extadd_pairwise_i16x8_u(x: simd::i16x8) -> simd::i32x4;
     #[link_name = "llvm.wasm.alltrue.v4i32"]
     fn llvm_i32x4_all_true(x: simd::i32x4) -> i32;

crates/core_arch/src/x86/avx.rs

@@ -573,7 +573,7 @@ pub fn _mm256_blendv_ps(a: __m256, b: __m256, c: __m256) -> __m256 {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_dp_ps<const IMM8: i32>(a: __m256, b: __m256) -> __m256 {
     static_assert_uimm_bits!(IMM8, 8);
-    unsafe { vdpps(a, b, IMM8) }
+    unsafe { vdpps(a, b, IMM8 as i8) }
 }
 
 /// Horizontal addition of adjacent pairs in the two packed vectors
@@ -3043,7 +3043,7 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx.round.ps.256"]
     fn roundps256(a: __m256, b: i32) -> __m256;
     #[link_name = "llvm.x86.avx.dp.ps.256"]
-    fn vdpps(a: __m256, b: __m256, imm8: i32) -> __m256;
+    fn vdpps(a: __m256, b: __m256, imm8: i8) -> __m256;
     #[link_name = "llvm.x86.avx.hadd.pd.256"]
     fn vhaddpd(a: __m256d, b: __m256d) -> __m256d;
     #[link_name = "llvm.x86.avx.hadd.ps.256"]

crates/core_arch/src/x86/avx2.rs

@@ -2146,7 +2146,7 @@ pub fn _mm256_movemask_epi8(a: __m256i) -> i32 {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_mpsadbw_epu8<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
     static_assert_uimm_bits!(IMM8, 8);
-    unsafe { transmute(mpsadbw(a.as_u8x32(), b.as_u8x32(), IMM8)) }
+    unsafe { transmute(mpsadbw(a.as_u8x32(), b.as_u8x32(), IMM8 as i8)) }
 }
 
 /// Multiplies the low 32-bit integers from each packed 64-bit element in
@@ -3800,7 +3800,7 @@ unsafe extern "C" {
     #[link_name = "llvm.x86.avx2.maskstore.q.256"]
     fn maskstoreq256(mem_addr: *mut i8, mask: i64x4, a: i64x4);
     #[link_name = "llvm.x86.avx2.mpsadbw"]
-    fn mpsadbw(a: u8x32, b: u8x32, imm8: i32) -> u16x16;
+    fn mpsadbw(a: u8x32, b: u8x32, imm8: i8) -> u16x16;
     #[link_name = "llvm.x86.avx2.pmul.hr.sw"]
     fn pmulhrsw(a: i16x16, b: i16x16) -> i16x16;
     #[link_name = "llvm.x86.avx2.packsswb"]