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bump mipsel isa leval and enable fpxx #48874

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Merged
merged 3 commits into from
Mar 14, 2018
Merged

bump mipsel isa leval and enable fpxx #48874

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f53f2fa
librustc_back: bump ISA level of mipsel targets to mips32r2
jcowgill Mar 8, 2018
fccaf25
librustc_back: enable fpxx on 32-bit hardfloat mips targets
jcowgill Mar 8, 2018
0711a7a
librustc_trans: add fp64 to mips features whitelist
jcowgill Mar 8, 2018
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librustc_back: enable fpxx on 32-bit hardfloat mips targets 
See this page for details about FPXX:
https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking

Using FPXX is the most compatible floating point mode available and
allows the generated code to work in both FR0 and FR1 modes of the
processor. Using MSA (MIPS SIMD) requires FR1, so to use any MSA code we
need a compatible floating point mode.

This commit also sets nooddspreg (disabling the use of odd numbered
single precision float registers) as recommended when enabling FPXX.
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@jcowgill
jcowgill committed Mar 8, 2018
commit fccaf252df7d5426ae5b0d8b8359357fe526fc58
2 changes: 1 addition & 1 deletion src/librustc_back/target/mips_unknown_linux_gnu.rs
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Expand Up @@ -25,7 +25,7 @@ pub fn target() -> TargetResult {
linker_flavor: LinkerFlavor::Gcc,
options: TargetOptions {
cpu: "mips32r2".to_string(),
features: "+mips32r2".to_string(),
features: "+mips32r2,+fpxx,+nooddspreg".to_string(),
max_atomic_width: Some(32),

// see #36994
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2 changes: 1 addition & 1 deletion src/librustc_back/target/mipsel_unknown_linux_gnu.rs
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Expand Up @@ -26,7 +26,7 @@ pub fn target() -> TargetResult {

options: TargetOptions {
cpu: "mips32r2".to_string(),
features: "+mips32r2".to_string(),
features: "+mips32r2,+fpxx,+nooddspreg".to_string(),
max_atomic_width: Some(32),

// see #36994
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