Add fused multiply-add vector intrinsics #32066
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This defines the following intrinsics for 128 and 256 bit vectors of f32 and f64: * `fmadd` * `fmaddsub` * `fmsub` * `fmsubadd` * `fnmadd` * `fnmsub` The `_sd` and `_ss` variants are not included yet. Intel intrinsic reference: https://software.intel.com/en-us/node/523929 The intrinsics there are listed under AVX2, but in the Intel Intrinsic Guide they are part of the "FMA" technology, and LLVM puts them under FMA, not AVX2.
The file it generates had been modified, but instead the generator should have been modified, and the file regenerated. This merges the modifications into the template in the generator.
The exact command used was:
$ cd src/etc/platform-intrinsics/x86
$ python2 ../generator.py --format compiler-defs -i info.json \
sse.json sse2.json sse3.json ssse3.json sse41.json sse42.json \
avx.json avx2.json fma.json \
> ../../../librustc_platform_intrinsics/x86.rs
|
cc @huonw, you wrote most of the other intrinsics and SIMD support, can you please have a look if you have the time? |
bors
added a commit
that referenced
this pull request
Mar 7, 2016
This adds support for fused multiply-add and multiply-subtract vector intrinsics for 128 and 256-bit vectors of `f32` and `f64`. These correspond to the intrinsics [listed here](https://software.intel.com/en-us/node/523929) except for the `_ss` and `_sd` variants. The intrinsics added are: * `fmadd` * `fmaddsub` * `fmsub` * `fmsubadd` * `fnmadd` * `fnmsub` The “fma” target feature must be enabled by passing `-C target-feature=+fma` to rustc when using these, otherwise LLVM will complain. I verified locally that the `x86_mm256_fmadd_ps` and `x86_mm256_fmsub_ps` work.
|
Is there a reason why fma 512 wasn't included? IIRC llvm also has support for these. |
|
512-bit FMA instructions are part of AVX-512, not of the FMA instructions. I don’t have a CPU that supports AVX-512. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This adds support for fused multiply-add and multiply-subtract vector intrinsics for 128 and 256-bit vectors of
f32andf64. These correspond to the intrinsics listed here except for the_ssand_sdvariants. The intrinsics added are:fmaddfmaddsubfmsubfmsubaddfnmaddfnmsubThe “fma” target feature must be enabled by passing
-C target-feature=+fmato rustc when using these, otherwise LLVM will complain.I verified locally that the
x86_mm256_fmadd_psandx86_mm256_fmsub_pswork.