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Rollup of 5 pull requests #126824

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merged 19 commits into from
Jun 22, 2024
Merged

Rollup of 5 pull requests #126824

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9fd7784
Fix `...` in multline code-skips in suggestions
estebank Jun 20, 2024
a12f541
Implement new command execution logic
Kobzol Jun 20, 2024
949e667
Remove `run_quiet`
Kobzol Jun 20, 2024
e933cfb
Remove `run_quiet_delaying_failure`
Kobzol Jun 20, 2024
0de7b92
Remove `run_delaying_failure`
Kobzol Jun 20, 2024
5c4318d
Implement `run_cmd` in terms of `run_tracked`
Kobzol Jun 20, 2024
c152934
Remove unused import
Kobzol Jun 20, 2024
3fe4d13
Appease `clippy`
Kobzol Jun 20, 2024
bc12972
Slightly refactor the dumping of HIR analysis data
fmease Jun 19, 2024
753fb07
Add `f16` inline ASM support for 32-bit ARM
beetrees Jun 16, 2024
38bd7a0
Add `#[rustc_dump_{predicates,item_bounds}]`
fmease Jun 19, 2024
250586c
Wrap std `Output` in `CommandOutput`
Kobzol Jun 22, 2024
d9962bb
Make `read_dir` method take a mutable callback
GuillaumeGomez Jun 22, 2024
e7dfd4a
Migrate `run-make/inline-always-many-cgu` to `rmake.rs`
GuillaumeGomez Jun 22, 2024
07e8b3a
Rollup merge of #126555 - beetrees:f16-inline-asm-arm, r=Amanieu
GuillaumeGomez Jun 22, 2024
3ed2cd7
Rollup merge of #126686 - fmease:dump-preds-n-item-bounds, r=compiler…
GuillaumeGomez Jun 22, 2024
399c5ca
Rollup merge of #126723 - estebank:dot-dot-dot, r=Nadrieril
GuillaumeGomez Jun 22, 2024
25bcc7d
Rollup merge of #126731 - Kobzol:bootstrap-cmd-refactor, r=onur-ozkan
GuillaumeGomez Jun 22, 2024
d265538
Rollup merge of #126823 - GuillaumeGomez:migrate-run-make-inline-alwa…
GuillaumeGomez Jun 22, 2024
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Add f16 inline ASM support for 32-bit ARM
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@beetrees
beetrees committed Jun 21, 2024
commit 753fb070bb2962fc6f909c6d7adf568b6b28bbb5
39 changes: 39 additions & 0 deletions compiler/rustc_codegen_llvm/src/asm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1020,6 +1020,19 @@ fn llvm_fixup_input<'ll, 'tcx>(
value
}
}
(
InlineAsmRegClass::Arm(
ArmInlineAsmRegClass::dreg
| ArmInlineAsmRegClass::dreg_low8
| ArmInlineAsmRegClass::dreg_low16
| ArmInlineAsmRegClass::qreg
| ArmInlineAsmRegClass::qreg_low4
| ArmInlineAsmRegClass::qreg_low8,
),
Abi::Vector { element, count: count @ (4 | 8) },
) if element.primitive() == Primitive::Float(Float::F16) => {
bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
}
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
match s.primitive() {
// MIPS only supports register-length arithmetics.
Expand Down Expand Up @@ -1130,6 +1143,19 @@ fn llvm_fixup_output<'ll, 'tcx>(
value
}
}
(
InlineAsmRegClass::Arm(
ArmInlineAsmRegClass::dreg
| ArmInlineAsmRegClass::dreg_low8
| ArmInlineAsmRegClass::dreg_low16
| ArmInlineAsmRegClass::qreg
| ArmInlineAsmRegClass::qreg_low4
| ArmInlineAsmRegClass::qreg_low8,
),
Abi::Vector { element, count: count @ (4 | 8) },
) if element.primitive() == Primitive::Float(Float::F16) => {
bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
}
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
match s.primitive() {
// MIPS only supports register-length arithmetics.
Expand Down Expand Up @@ -1233,6 +1259,19 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
layout.llvm_type(cx)
}
}
(
InlineAsmRegClass::Arm(
ArmInlineAsmRegClass::dreg
| ArmInlineAsmRegClass::dreg_low8
| ArmInlineAsmRegClass::dreg_low16
| ArmInlineAsmRegClass::qreg
| ArmInlineAsmRegClass::qreg_low4
| ArmInlineAsmRegClass::qreg_low8,
),
Abi::Vector { element, count: count @ (4 | 8) },
) if element.primitive() == Primitive::Float(Float::F16) => {
cx.type_vector(cx.type_i16(), count)
}
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
match s.primitive() {
// MIPS only supports register-length arithmetics.
Expand Down
12 changes: 7 additions & 5 deletions compiler/rustc_target/src/asm/arm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -47,16 +47,18 @@ impl ArmInlineAsmRegClass {
_arch: InlineAsmArch,
) -> &'static [(InlineAsmType, Option<Symbol>)] {
match self {
Self::reg => types! { _: I8, I16, I32, F32; },
Self::sreg | Self::sreg_low16 => types! { vfp2: I32, F32; },
Self::reg => types! { _: I8, I16, I32, F16, F32; },
Self::sreg | Self::sreg_low16 => types! { vfp2: I32, F16, F32; },
Self::dreg_low16 | Self::dreg_low8 => types! {
vfp2: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
vfp2: I64, F64;
neon: VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF16(4), VecF32(2);
},
Self::dreg => types! {
d32: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
d32: I64, F64;
neon: VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF16(4), VecF32(2);
},
Self::qreg | Self::qreg_low8 | Self::qreg_low4 => types! {
neon: VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4);
neon: VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF16(8), VecF32(4);
},
}
}
Expand Down
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