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Issues list

c_char signedness doesn't match with Clang's default on various no-std and tier 3 targets A-ABI Area: Concerning the application binary interface (ABI) C-bug Category: This is a bug. O-AArch64 Armv8-A or later processors in AArch64 mode O-android Operating system: Android O-Arm Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state O-bare-metal Target: Rust without an operating system O-csky Target: glaCSKY above covers over me~ O-hermit Operating System: Hermit O-illumos the other shiny OS O-riscv Target: RISC-V architecture T-libs Relevant to the library team, which will review and decide on the PR/issue.
#129945 opened Sep 3, 2024 by taiki-e
1
5
RISC-V Extension P intrinsics use invalid instruction format A-inline-assembly Area: Inline assembly (`asm!(…)`) C-bug Category: This is a bug. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#129593 opened Aug 25, 2024 by dingxiangfei2009
3
interrupted by SIGSEGV on riscv64 C-bug Category: This is a bug. I-crash Issue: The compiler crashes (SIGSEGV, SIGABRT, etc). Use I-ICE instead when the compiler panics. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#129268 opened Aug 19, 2024 by alitariq4589
13
rustc SIGSEGV compiling rug 1.24.1 crate on RISC-V Armbian 24.5.0 C-discussion Category: Discussion or questions that doesn't represent real issues. I-crash Issue: The compiler crashes (SIGSEGV, SIGABRT, etc). Use I-ICE instead when the compiler panics. O-riscv Target: RISC-V architecture
#127180 opened Jun 30, 2024 by mathsDOTearth
4
asm! should actually understand "can you address this register?" A-inline-assembly Area: Inline assembly (`asm!(…)`) C-cleanup Category: PRs that clean code up or issues documenting cleanup. O-AArch64 Armv8-A or later processors in AArch64 mode O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. T-libs Relevant to the library team, which will review and decide on the PR/issue.
#126890 opened Jun 24, 2024 by workingjubilee
error: Error loading target specification: Could not find specification for target "riscv64-unknown-linux-gnu". A-targets Area: Concerning the implications of different compiler targets C-discussion Category: Discussion or questions that doesn't represent real issues. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#123161 opened Mar 28, 2024 by andreas-schwab
24
Unable to compile rust for riscv32imc-unknown-none-elf with clang 19.0.0git C-bug Category: This is a bug. E-needs-test Call for participation: An issue has been fixed and does not reproduce, but no test has been added. O-riscv Target: RISC-V architecture T-bootstrap Relevant to the bootstrap subteam: Rust's build system (x.py and src/bootstrap)
#121371 opened Feb 21, 2024 by erickt
4
libcore on riscv64gc-unknown-none-elf contains problematic .sdata section A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. C-bug Category: This is a bug. I-heavy Issue: Problems and improvements with respect to binary size of generated code. O-riscv Target: RISC-V architecture
#120685 opened Feb 5, 2024 by dreiss
4
riscv64-unknown-freebsd patches backtrace support out O-freebsd Operating system: FreeBSD O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#117183 opened Oct 25, 2023 by estebank
1
Errors compiling libc using rust 1.73.0 on riscv64/ubuntu:focal docker image - works with 1.72.1 A-linkage Area: linking into static, shared libraries and binaries C-bug Category: This is a bug. O-riscv Target: RISC-V architecture P-high High priority regression-from-stable-to-stable Performance or correctness regression from one stable version to another. regression-untriaged Untriaged performance or correctness regression. T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#117101 opened Oct 23, 2023 by emlowe
5
The sparc64, riscv64, loongarch64 extern "C" fn ABIs are all wrong when aligned/packed structs are involved A-ABI Area: Concerning the application binary interface (ABI) I-unsound Issue: A soundness hole (worst kind of bug), see: https://en.wikipedia.org/wiki/Soundness O-loongarch Target: LoongArch (LA32R, LA32S, LA64) O-riscv Target: RISC-V architecture O-SPARC Target: SPARC processors P-medium Medium priority T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#115609 opened Sep 6, 2023 by RalfJung
23
RISC-V Codegen Problem with type information A-codegen Area: Code generation A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. C-bug Category: This is a bug. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#114508 opened Aug 5, 2023 by coastalwhite
@SpriteOvO
18
Suboptimal dual-exit code gen on RISC-V A-codegen Area: Code generation C-bug Category: This is a bug. I-slow Issue: Problems and improvements with respect to performance of generated code. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#113346 opened Jul 4, 2023 by tommythorn
liballoc built with -Csplit-debuginfo=unpacked despite not being supported on riscv32imc-unknown-none-elf A-debuginfo Area: Debugging information in compiled programs (DWARF, PDB, etc.) O-riscv Target: RISC-V architecture T-bootstrap Relevant to the bootstrap subteam: Rust's build system (x.py and src/bootstrap)
#112406 opened Jun 7, 2023 by tmandry
1
Tracking Issue for riscv-interrupt-{m,s} ABIs A-ABI Area: Concerning the application binary interface (ABI) C-tracking-issue Category: A tracking issue for an RFC or an unstable feature. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#111889 opened May 23, 2023 by sethp
1 of 3 tasks
1
Compilation error about RISC-V H extension C-bug Category: This is a bug. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#111637 opened May 16, 2023 by KuangjuX
13
Tracking Issue for stdarch_riscv_feature_detection C-tracking-issue Category: A tracking issue for an RFC or an unstable feature. O-riscv Target: RISC-V architecture T-libs-api Relevant to the library API team, which will review and decide on the PR/issue.
#111192 opened May 4, 2023 by Amanieu
2 tasks
2
How to generate one instruction only when asm! is used in naked functions? A-inline-assembly Area: Inline assembly (`asm!(…)`) I-heavy Issue: Problems and improvements with respect to binary size of generated code. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#96037 opened Apr 14, 2022 by luojia65
7
Uses non-existent FreeBSD 11 syscall ABI for FreeBSD RISC-V C-bug Category: This is a bug. O-freebsd Operating system: FreeBSD O-riscv Target: RISC-V architecture
#92466 opened Dec 31, 2021 by jrtc27
4
"-Zbuild_std" produces a broken std on riscv32gc-unknown-linux-gnu C-bug Category: This is a bug. O-riscv Target: RISC-V architecture
#88995 opened Sep 16, 2021 by sajattack
6
Regression: undefined symbol __atomic_load_4 on risvc32imac-unknown-none-elf A-atomic Area: Atomics, barriers, and sync primitives A-LTO Area: Link-time optimization (LTO) C-bug Category: This is a bug. ICEBreaker-Cleanup-Crew Helping to "clean up" bugs with minimal examples and bisections O-riscv Target: RISC-V architecture P-medium Medium priority regression-from-stable-to-stable Performance or correctness regression from one stable version to another.
#85736 opened May 27, 2021 by xobs
10
global_asm! macro causes non-fatal errors to be printed during compilation for some RISC-V extension instructions when targeting the GC extensions A-inline-assembly Area: Inline assembly (`asm!(…)`) A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. C-bug Category: This is a bug. F-asm `#![feature(asm)]` (not `llvm_asm`) O-riscv Target: RISC-V architecture
#80608 opened Jan 2, 2021 by repnop
6
Use fclass.{s|d|q} instruction for float point classification in RISC-V targets A-floating-point Area: Floating point numbers and arithmetic C-enhancement Category: An issue proposing an enhancement or a PR with one. I-slow Issue: Problems and improvements with respect to performance of generated code. O-riscv Target: RISC-V architecture T-libs Relevant to the library team, which will review and decide on the PR/issue.
#73015 opened Jun 5, 2020 by luojia65
6
oreboot won't build for riscv64: __atomic_{load,store}_16 are not defined C-bug Category: This is a bug. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. WG-embedded Working group: Embedded systems
#66240 opened Nov 9, 2019 by rminnich
9
compiler_fence may emit machine code A-atomic Area: Atomics, barriers, and sync primitives A-codegen Area: Code generation A-docs Area: documentation for any part of the project, including the compiler, standard library, and tools A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. C-bug Category: This is a bug. I-heavy Issue: Problems and improvements with respect to binary size of generated code. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
#62256 opened Jun 30, 2019 by Disasm
14
ProTip! Follow long discussions with comments:>50.