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Description
This issue tracks the implementation of all the intrinsics linked to the Ratified RISC-V Extensions. The, not yet stable intrinsics are behind the riscv_ext_intrinsics
nightly feature.
Steps
- Implement all extensions in
stdarch
- Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
-
Zkr
. Entropy source extension - Bit-Manipulation
- Zicntr and Zihpm
- Zicsr
-
Half-Precision -
Float in Integer - Vector Extension
- Adjust module level documentation
- Stabilization PR
Unresolved Questions
How to deal with instructions that are already dealt with by LLVM intrinsics and library features (e.g.cpop
andu*::count_ones
)? Include them or not?- Use
usize
for riscv32 orriscv64
specific intrinsics or useu32
andu64
respectively? How to deal with intrinsics involving immediate values?Use theasm_const
feature outlined in Tracking Issue for asm_const #93332.Use the trick described in Implement all x86 vendor intrinsics stdarch#40 and illustrated in_mm_cmpestri
.
- How to deal with CSR registers?
- Can we source titles and descriptions from the specifications? License issues?
- Dealing with the Vector extension is very difficult due to dynamically sized registers (RFC: Add a scalable representation to allow support for scalable vectors rfcs#3268).
Implementation History
- Implement RISC-V Zk intrinsics stdarch#1453. Implements the Zk extension, except Entropy Source and Zkt.
- Implement RISC-V Zb intrinsics stdarch#1461. Implements the Zb extension.
- Stabilize Ratified RISC-V Target Features #116485. Stabilizes several RISC-V target features.
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Area: SIMD (Single Instruction Multiple Data)Area: Floating point numbers and arithmeticArea: Enabling/disabling target features like AVX, Neon, etc.Category: An issue tracking the progress of sth. like the implementation of an RFCTarget: RISC-V architectureRelevant to the library API team, which will review and decide on the PR/issue.
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